Zeyad Aklah*
| Amean Al-Safi | Hussein T. Hassan
© 2024 The authors. This article is published by IIETA and is licensed under the CC BY 4.0 license (http://creativecommons.org/licenses/by/4.0/).
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This paper explores the field of FPGA implementation and emulation of memristor devices, providing insights into the advancements, challenges, and future directions. The paper discusses various techniques used for FPGA-based memristor emulation, emphasizing the importance of accurate memristor modeling and performance evaluation. It identifies challenges in the field, including improving accuracy, scalability, real-time adaptation, standardization, integration with design tools, and exploring novel applications. Additionally, the results of the study show that FPGAs are one of the viable solutions for emulating memristors. The study concludes that FPGA based memristor emulation holds a promise for studying memristor-based circuits and systems, with potential applications in neuromorphic computing, machine learning accelerators, and analog/mixed-signal circuit design.
memristor, FPGA, emulation, modelling, neuromorphic computing
The rapid advancements in semiconductor technology have driven the need for novel electronic devices with improved performance, energy efficiency, and functionality. Memristors, short for memory resistors, have emerged as a promising technology that exhibits unique properties and capabilities. In contrast to the classical electronic elements like resistors, capacitors, and inductors, memristors possess the ability to retain and store information in the form of resistance variations [1]. This characteristic has attracted considerable attention as it opens up exciting possibilities for the development of new computing paradigms, memory systems, and signal processing applications.
The integration and fabrication of physical memristor devices into existing electronic systems presents several challenges, including fabrication complexity, scalability, and compatibility [2]. In response to these challenges, researchers have explored alternative approaches such as FPGA-based implementation and emulation of memristor devices [3-12]. FPGAs, Field-Programmable Gate Arrays, supply adaptable and easily reconfigurable platforms that can mimic the behavior of complex circuits and devices.
FPGA-based emulation of memristor devices involves creating a digital model of the memristor’s behavior and implementing it on an FPGA [11]. This approach allows designers to study and analyze the characteristics of memristors without relying on physical prototypes. For instance, FPGA-based emulation techniques include LUT, look-up table, based emulation [4], where the behavior of the memristor is stored in a lookup table within the FPGA, and HDL (hardware description language) modeling, where the behavior is described using specialized programming languages such as VHDL or Verilog. Alternatively, FPGA-based implementation of memristor devices aims to physically realize memristor behavior using the reconfigurable resources available in FPGAs [3]. This approach involves mapping the memristor’s electrical characteristics and functionality onto the FPGA’s logic elements, routing resources, and configurable interconnects. Specialized reconfigurable architectures designed specifically for memristor circuits have also been proposed [13], leveraging the unique properties of memristors to enhance performance and energy efficiency.
The main need for FPGA based memristor emulation is to allow designers to overcome the limitations associated with physical memristor devices, including fabrication costs, limited availability, and experimental constraints. FPGAs provide a flexible and accessible platform for rapid prototyping, testing, and evaluation of memristor-based systems and circuits.
The objective of this study is to explore the advancements, challenges, and future prospects of using FPGAs for the implementation and emulation of memristor devices. It delves into the various FPGA-based emulation techniques, such as LUT-based emulation and HDL modeling, highlighting their advantages, limitations, and trade-offs. Additionally, it will investigate FPGA-based implementation methodologies, including mapping memristor behavior to FPGA primitives and leveraging specialized FPGA architectures. The paper will also discuss the performance evaluation and benchmarking approaches employed by designers to assess the effectiveness of FPGA-based memristor implementations. Furthermore, it will address the challenges associated with FPGA-based approaches, such as resource limitations, design complexity, and the need for accurate memristor models. We will explore potential strategies and research directions for overcoming these challenges and optimizing FPGA-based memristor implementations. Lastly, the applications and impact of FPGA-based emulation and implementation of memristor devices in various domains will be discussed, such as neuromorphic computing, machine learning, hardware security, and reconfigurable computing.
Through this paper, we aim to provide insights and guidance to researchers, engineers, and practitioners interested in exploring the potential of FPGAs for memristor-based technologies.
Memristors are a class of electronic devices that have gained considerable interest recently due to their distinct characteristics and possible uses. Coined by Professor Leon Chua in 1971, the term” memristor” refers to a passive two-terminal device that displays a relationship between electric charge and magnetic flux linking the device that is non-linear [14]. Unlike traditional electronic components such as resistors, capacitors, and inductors, memristors possess the ability to retain and store information in the form of resistance variations [15-17].
Memristors are characterized by their ability to change their resistance value based on the electrical current, magnitude and direction, passing through them. This phenomenon, known as resistance switching, allows memristors to exhibit multiple resistance states, that can be used to store and process information [16]. The memristor’s resistance state can be altered by applying a suitable voltage or current stimulus, leading to changes in its conductance and resistance levels. Importantly, these resistance states are non-volatile, meaning they persist even when the power supply is disconnected [18].
The underlying mechanism behind memristor behavior involves the migration and redistribution of defects or ions within the memristive material [19]. This process, known as the migration of dopant atoms, results in changes in the conductive pathways within the material, leading to alterations in resistance [20]. Memristors can exhibit different types of resistance switching behaviors, including unipolar and bipolar switching, depending on the specific materials and operating conditions [21, 22].
The distinctive attributes of memristors that make them appealing for various applications. In neuromorphic computing field, memristors have shown promise in emulating the synaptic behavior of biological neurons, enabling the advancement of energy-efficient and brain-inspired computing systems [23]. Memristors also hold potential in non-volatile memory applications, where they can provide high-density storage and faster access times compared to conventional memory technologies [20]. Additionally, memristors have been explored for applications in analog signal processing, where their resistance states can be exploited to perform complex mathematical operations [24].
Despite their potential, the integration and fabrication of physical memristor devices into existing electronic systems present several challenges [23]. Fabrication processes, scalability, and compatibility with established circuit design techniques are among the primary concerns [2]. As a result, researchers [3-5, 7] have explored alternative approaches to harness the benefits of memristor technology, including the use of FPGAs for memristor implementation and emulation.
2.1 Resistance switching and hysteresis
Memristor hysteresis refers to the phenomenon where the electrical resistance of a memristor depends not only on the instantaneous current or voltage applied to it but also on its past history [1]. That means, the memristor’s state resistance depends on the path it takes to reach its current state. This behavior is analogous to the hysteresis observed in magnetic materials, where the magnetic field strength depends on the previous magnetic history [25].
When a memristor is subjected to an increasing voltage or current stimulus, it changes from a low resistance state (LRS) to a high resistance state (HRS) [26]. This transition occurs at a particular voltage or current level, known as the SET threshold [27]. Conversely, when the voltage or current is decreased, the memristor transitions from HRS to LRS at a different voltage or current threshold, called the RESET threshold. The existence of these distinct threshold voltages or currents forms the basis of the hysteresis behavior in memristors [26].
The hysteresis in memristors can be visualized on a current-voltage (I-V) graph as depicted in Figure 1 (d). When the applied voltage or current is swept from a negative value to a positive one and back, the I-V curve displays a loop-like curve. This loop represents the hysteresis loop, with the ascending branch corresponding to the SET process and the descending branch corresponding to the RESET process. The area enclosed by the hysteresis loop is an indication of the energy consumed during the resistance switching operation [1].
Figure 1. (a) memristor symbol, (b) HP memristor model structure, (c) memristor equivalent circuit representation, (d) memristor’s I-V characteristics (hysteresis loop)
The hysteresis phenomenon in memristors has significant implications for their applications. One of the key advantages of hysteresis is that it allows the memristor to retain its resistance state even when the applied voltage or current is removed [28]. This non-volatile property makes memristors suitable for applications in non-volatile memory, where data can be stored even in the absence of power [20]. Moreover, the resistance switching characteristics, combined with the hysteresis, allow memristors to emulate synaptic behavior, which is crucial for neuromorphic computing applications [16]
2.2 Memristor hysteresis in emulation process
The emulation of memristor hysteresis is a crucial aspect when simulating memristor behavior using digital models or implementing memristor functionality on FPGAs. Capturing hysteresis in the emulation process is essential to replicate the history dependent behavior of physical memristor devices.
To emulate memristor hysteresis, various mathematical formulations and models can be employed. These models aim to reproduce the hysteresis loop and predict the memristor’s resistance state based on its electrical history. The choice of the model depends on the specific characteristics of the memristor being emulated and the desired level of accuracy.
One common approach to capture hysteresis in memristor emulation is through the use of window functions. Window functions define different thresholds for the SET and RESET processes, similar to the voltage or current thresholds observed in physical memristors. These thresholds determine the transition points between the HRS and LRS. By incorporating window functions into the emulation process, the resistance switching behavior and hysteresis can be effectively reproduced.
Another approach involves using sigmoidal functions or piecewise linear functions to model the resistance variation in response to the applied current or voltage. These functions map the input stimuli to the corresponding resistance states, considering the previous memristor’s history. By carefully selecting the parameters of these functions, such as slope and threshold values, the hysteresis behavior can be represented in the emulation.
In addition to the mathematical models, other techniques can be employed to capture hysteresis in memristor emulation. For instance, data-driven approaches based on machine learning algorithms can be utilized to learn the hysteresis behavior from experimental data or physical memristor measurements. These algorithms can be used to predict the resistance state based on the input history, allowing for emulation of hysteresis.
It is crucial to emphasize that the accuracy of the memristor hysteresis emulation depends not only on the chosen model but also on the fidelity of the emulation platform. FPGAs have been used for memristor emulation due to their reconfigurable nature and ability to mimic complex circuits. The selection of appropriate FPGA resources, such as look-up tables, digital signal processing blocks, or programmable interconnects, is crucial to achieve emulation of memristor hysteresis.
Furthermore, the time scales involved in the resistance switching process should be considered in the emulation. Physical memristors exhibit varying switching speeds, and capturing this behavior accurately is essential for faithful emulation. The choice of simulation or emulation techniques, such as discrete-time models or real-time simulations, should be based on the desired time resolution and the specific dynamics of the memristor being emulated.
A few research groups have developed FPGA-based emulation platforms for memristor devices. These platforms utilize the reconfigurable nature of FPGAs to implement digital models that capture the essential characteristics of memristors, including resistance switching and hysteresis. By programming the FPGA, designers can simulate the behavior of memristors and investigate their potential applications in various domains.
3.1 Advanced mathematical models
In the field of FPGA-based emulation of memristor devices, advanced mathematical systems have been established to capture the complex behavior exhibited by memristors. These models provide an enhanced comprehension of the underlying mechanisms. Several notable examples of advanced mathematical models for memristor emulation have been proposed, as discussed below.
3.1.1 Extended SPICE models
SPICE, which is an abbreviation for Simulation Program with Integrated Circuit Emphasis, is a well-known simulation tools. Several SPICE macromodels have been suggested for linear [29, 30] and nonlinear ion drift models [31]. In the study [32], the relationship between current and voltage is established using a hyperbolic sine function, while the derivative of the state variable is represented by an exponent. The other model called TEAM [33] utilizes polynomials to capture the behavior of the system. In general, SPICE macromodels requires more computational resources compared to Verilog-A model, which maintains a comparable level of accuracy in the results it produces [32].
3.1.2 Piecewise-linear models
Piecewise-linear models provide an alternative approach to describe the behavior of memristors [34]. These models divide the voltage-current characteristic of the memristor into linear segments, capturing the essential non-linear behavior with a series of linear equations [35]. By fitting experimental data to these piecewise-linear segments, designers can achieve emulation of memristor behavior on FPGA platforms [36]. This modeling technique has been successfully employed in FPGA-based memristor emulation to study the impact of non-linear dynamics on system-level performance [37].
3.1.3 Non-linear differential equations
Non-linear differential equations provide a fundamental approach to model the dynamics of memristor devices. These equations describe the time-varying relationship between voltage and current and capture the essential non-linear behavior observed in memristors. Researchers have developed advanced numerical methods and algorithms to solve these non-linear differential equations efficiently on FPGA platforms [38]. By implementing these equations on FPGAs, researchers can precisely emulate the dynamic behaviors of memristors and study their impact on circuit performance.
3.2 Hardware-software co-design
Hardware-software co-design plays an essential part in ensuring efficiency and emulation effectivity of memristor devices on FPGA platforms. This approach leverages the strengths of both hardware and software components to achieve optimal performance, flexibility, and accuracy in memristor emulation. Below some examples of hardware-software co-design methodologies for memristor emulation have been proposed.
3.2.1 High-level synthesis (HLS)
High-level synthesis techniques enable the design of memristor emulators at a higher level of abstraction, allowing for faster development and optimization. Researchers have utilized HLS tools such as Vivado HLS or Intel HLS Compiler to convert high-level hardware description languages (HDL) into optimized hardware designs suitable for FPGA implementation [39]. By utilizing HLS, designers can achieve faster development cycles and explore different architectural optimizations.
3.2.2 Custom instruction set architectures (ISA)
To enhance the performance of memristor emulators on FPGAs, custom instruction set architectures (ISA) have been developed. These ISAs are tailored to accelerate specific memristor operations, resulting in flexible emulation. For example, researchers have proposed custom instructions for memristor read/write operations, voltage-controlled switching, or specific mathematical functions related to memristor behavior [40-42]. By implementing these custom ISAs on FPGA platforms, designers can achieve more flexibility in memristor emulation.
3.2.3 Hybrid emulation platforms
Hybrid emulation platforms combine the power of FPGA-based hardware acceleration with the flexibility and versatility of software simulations. These platforms integrate FPGA-based emulators with software-based memristor models or simulators to achieve a balance between speed and accuracy. For instance, researchers have developed frameworks that enable co-simulation between FPGA platforms and software memristor models, allowing for detailed memristor behavior to be simulated in software while leveraging FPGA acceleration for faster execution [43-45]. By utilizing hybrid emulation platforms, designers can explore larger and more complex memristor systems while maintaining accurate and efficient emulation.
3.2.4 Runtime reconfigurability
Runtime reconfigurability is another key aspect of hardware-software co-design in memristor emulation. It allows for dynamic reconfiguration of the FPGA fabric during runtime to adapt to varying emulation requirements or to implement different memristor models or algorithms on the fly. Researchers have explored runtime reconfigurable FPGA architectures and algorithms to enable efficient emulation of memristor devices with varying characteristics or to support real-time adaptation in response to dynamic system behavior [46, 47]. This capability enhances the flexibility and versatility of memristor emulation on FPGA platforms, enabling designers to explore a wide range of memristor-based systems and applications.
3.3 Integration of real-time feedback
The integration of real-time feedback is a significant aspect of FPGA-based emulation of memristor devices, as it allows for dynamic adaptation and control of the emulated memristor behavior. Real-time feedback enables the emulation platform to respond to changing conditions or external stimuli, enhancing the accuracy and versatility of the emulation process. Several notable examples of integrating real-time feedback in FPGA-based memristor emulation have been explored, as discussed below.
3.3.1 Adaptive control strategies
Adaptive control strategies are employed to dynamically adjust the emulated memristor’s behavior based on feedback from the system or the environment. These strategies aim to optimize the emulation accuracy by continuously updating the memristor model parameters or adjusting the input signals to match the desired behavior. For instance, researchers have proposed adaptive control algorithms such as PID, proportional-integral-derivative, controllers or fuzzy logic controllers to regulate the memristor’s conductance or switching dynamics based on real-time feedback signals [48, 49]. Additionally, researchers have developed closed-loop systems that employ Kalman filters or neural networks to adaptively adjust the memristor model parameters based on real-time feedback from the emulated system [50]. By integrating adaptive control strategies, FPGA-based memristor emulators can emulate a wide range of memristor behaviors accurately.
3.3.2 Sensing and measurement circuits
In FPGA-based memristor emulation, real-time feedback often relies on the integration of sensing and measurement circuits to monitor the behavior of the emulated memristor. These circuits measure the memristor’s electrical properties, such as voltage, current, or resistance, and provide feedback signals to adapt the emulation accordingly. Researchers have developed custom measurement circuits and techniques, including voltage sensing circuits, current mirrors, or analog-to-digital converters (ADCs), to accurately capture the memristor behavior in real-time [51]. By integrating these sensing and measurement circuits, FPGA-based emulators can capture the memristor’s dynamic behavior and adjust the emulation parameters accordingly.
3.3.3 Hardware-in-the-loop (HIL) testing
Hardware-in-the-loop (HIL) testing techniques are utilized to validate the accuracy and performance of FPGA-based memristor emulators in real-time. HIL testing involves coupling the FPGA-based emulator with real hardware components or systems, creating a closed-loop system where the emulated memristor interacts with the physical world. Researchers have implemented HIL testing setups where the emulated memristor interacts with external circuits, sensors, or actuators, allowing for realtime validation and optimization of the emulation platform [52]. By integrating HIL testing, FPGA-based memristor emulators can be validated under realistic operating conditions, ensuring the reliability and accuracy of the emulation results.
3.4 FPGA-based implementation of memristor devices
Several research groups have made notable contributions to the implementation of memristor devices on FPGA platforms.
Example 1:
Zhang et al. [3] developed an FPGA-based memristor emulator that emulates the behavior of a memristor model described in the study [53]. The model is capable of generating a symmetrical double-loop hysteresis, represented by Eq. (1).
$I(t)=V(t)\left( \pm a \pm b \int_0^t V(\tau) d \tau\right)$ (1)
where, $V(t)$ is the normalized input voltage, $I(t)$ is the normalized output current, and $(a, b)$ are constants. To achieve memristive behavior, the condition $|b| \leq|a|$ must be maintained [3]. In order to implement the memristor model with threshold attribute, Zhang et al. suggested the conductance formula given in Eq. (2).
$G_t=\left\{\begin{array}{cc}G_{t-1}+c \times|V|^n & \text { if } \mathrm{V} \geq \mathrm{V}_{\mathrm{TH}} \\ G_{t-1} & \text { if }-\mathrm{V}_{\mathrm{TH}}<\mathrm{V}<\mathrm{V}_{\mathrm{TH}} \\ G_{t-1}-c \times|V|^n & \text { if } \mathrm{V}<-\mathrm{V}_{\mathrm{TH}} \\ G_{\text {init }} & \text { if reset }\end{array}\right.$ (2)
where, $G_{\text {init }}$ is the initial value of the memristor’s conductance, $G_t$ is the instantaneous conductance value, Gt−1 is the conductance value at the previous moment, VTH is the voltage threshold of the memristor, V is the input voltage, c is a parameter for fine-tuning the pinched hysteresis characteristics of the memristor, and n is the current adjustment parameter. The memristor’s conductance changes in response to positive or negative input voltage, either increasing or decreasing, when the absolute value of the input voltage exceeds the absolute value of the voltage threshold of the memristor. This behavior is in accordance with the physical properties inherent to a memristor [3].
To illustrate the implementation of the complete memristor model, the computational steps within the model are illustrated in Figure 2. First, the variables Ginit, VTH, Vin, T, n, and c, are initialized. Subsequently, the input voltage is compared with the threshold voltage level to determine the change in conductance. Then, the output current is obtained by multiplying the input voltage by the conductance value based on Ohm’s law. Lastly, the simulation time is assessed, and if the predefined duration is reached, the loop terminates; otherwise, the aforementioned steps are reapeted. The flowchart in Figure 3 shows the computational process within the memristor model, illustrating the realization of the entire model. Initially, the variables Ginit, VTH, Vin, T, n, and c are initialized. The input voltage is then compared with the voltage threshold to determine the alteration in conductivity. Using Ohm’s law, the input voltage is multiplied by the conductance value to obtain the output current. The process is repeated until reaching the designated simulation time, at which point the loop is exited [3].
Figure 2. FPGA based implementation of memristor model. (a) The model block diagram. (b) Circuit diagram of the reconfigurable memristor model [3]
Figure 3. Flowchart of memristor implementation [3]
Their work involved designing custom circuits for memristor, as shown in Figure 3 in a block diagram and data path. Once the input voltage traverses the register, it undergoes a comparison with a predefined voltage threshold. At the same time, Eq. (2) is employed to determine the output conductance, with the resulting calculation being allocated to the conductance through result comparison. The emulator was capable of reproducing the resistance switching behavior and hysteresis of memristor devices. Additionally, they implemented a memristor array of their model on FPGA to conduct storage of binary image binarization using artificial neural network
Example 2:
Tolba et al. [4] use FPGA to build a memristors emulater circuit for Binary Convolutional Neural Networks, utilizing a multi-bit XNOR gate as the primary component for binary convolution. The circuit incorporated a memristor-based pooling layer. The BCNN layer was achieved through a bitwise XNOR-cell followed by a wide NOR gate. The implemented design was implemented on Nexys4 FPGA, demonstrating less than 1% utilization resources have been used.
The two states of the memristor hysteresis loop were determined using the formula y=(±a±b)x and y=(±a∓b)x, while maintaining the condition |b|≤|a|. The implementation of memristor’s emulator circuits could be either voltage-controlled or current-controlled, depending on whether x(t) represented the input voltage and y(t) represented the output current, or vice versa. Additionally, a multi-state switching model (consisting of five states) was implemented to extend the two-state memristive model by incorporating additional conditions. The design utilized a 32-bit fixed-point representation, where the most significant bit (MSB) of ϕ selected between b and its inverted value. The output y was obtained by multiplying (a+b) with the input x. Figures 4 and 5 [4] illustrated the two-state and multi-state memristor models, demonstrating the I-V pinched hysteresis loops for the five memristor states and their corresponding representations.
Besides the above two examples, there are more approaches. For instance, the study [54] involved embedding fractional-order systems into FPGA hardware through the utilization of the Xilinx System Generator toolbox within MATLAB Simulink. It further examined a discrete model of a chaotic system featuring a fourth-order memristor with fractional-order dynamics, which was obtained through the conversion of the system’s differential version using a finite truncation method. The research also investigated the system's dynamics by exploring the Lyapunov exponents and conducting a bifurcation analysis of the discrete fractional-order memristor system.
Rajagopal et al. [55] introduced a new 4D no equilibrium memristor chaotic system and investigated its dynamic properties to demonstrate its chaotic behavior. They derived a fractional order model of the system from its integer model and analyzed its fractional order bifurcation property. The authors achieved synchronization of identical fractional order memristor chaotic systems utilizing genetically optimized PID controllers and adaptive sliding mode controllers. They conducted numerical simulations to confirm the theoretical findings and showcased the practical feasibility of the suggested system by implementing it on an FPGA.
Zhang et al. [56] presented a behavioral modelling of a general multivalued memristor using FPGA, claiming that its capability of exhibiting behavior similar to electrochemical metallization memories, whether continuous or discrete in nature. The suggested solution was implemented on a Xilinx ZYNQ-7000 FPGA XQ7Z020, utilizing less than 1% of the hardware resources. In order to assess the functionality of the propsed model, the study constructed a quantized artificial neural network using 8-valued memristors in FPGA.
Yu et al. [57] delved into the implementation of a PRNG, pseudo-random number generator, for neural network chaos-based systems on FPGAs. The research addressed the issue of chaotic degradation that was caused by numerical accuracy limitations and had the potential to significantly impact the PRNG’s performance. The authors suggested a PRNG featuring a feedback controller derived from a Hopfield neural network chaotic oscillator, with a neuron subjected to electromagnetic radiation. The magnetic flux through the cell membrane of the neuron was chosen as a feedback condition for the controller, creating disturbances among other neurons and preventing periodicity.
Alombah et al. [58] proposed a locally active memristor derived from a current-controlled generic memristor, demonstrating a broad locally active zone. The memristor based chaotic circuit consists of a memristor and an inductor was developed and numerically simulated using MATLAB then validated on FPGA.
Vourkas et al. [59] implemented a bipolar memristor device model represented in Eq. (3), described in the study [60]. The memristance R, in this model, varies at different rates based on the applied voltage, whether it is higher or lower than the threshold voltage vT. The threshold voltage is considered symmetric for both switching cases (SET and RESET). The memristance is limited by the upper and lower boundaries, denoted as RON, (RMIN) and ROFF (RMAX), respectively. The change in memristance is controlled by the step function (θ), indicating that R can only change within its limiting values. The change-rate constants α and β determine the rate of change when |v(t)|<v T and |v(t)|>vT, respectively.
$\begin{aligned} & R^{\prime}=\beta \cdot v+\frac{1}{2}(\alpha-\beta) \cdot\left(\left|v+v_T\right|\right. -\left|v-v_T\right| \cdot \theta\left(R-R_{O N}\right) \cdot \theta\left(R_{O F F}-R\right)\end{aligned}$ (3)
Figure 6 illustrates the block diagram of the memristor’s emulator model. The emulator takes inputs such as the top- and bottom-electrode voltages (VTE and VBE), the initial desired memristance (Rinit) obtained during the initialization phase. The output signal is the current memristance R. The model-specific parameters, including θ, β, and vT, were considered internal constants.
They employed Euler’s method to calculate the memristance (R) in the voltage controlled time-invariant memristor model. Euler’s method is a numerical approximation technique that allows for the iterative calculation of a function based on its derivative. In this case, it was used to estimate the change in memristance over time. The model could handle high-frequency input voltage signals by adjustable timestep (∆t). The time-step represents the interval between successive calculations of the memristance value. By appropriately adjusting ∆t, the model was able to capture and respond to rapid changes in the input voltage signals.
Figure 4. Hardware architecture of the memristor emulator, (a) 2-state memristor model and (b) multistates memristor model [4]
Figure 5. (a) I-V pinched hysteresis loops for 5-memristor states (b) memristor states when the input is cos(wt) [4]
Figure 6. Memristor emulator block diagram [4]
Table 1. Memristor based designs
|
Memristor Based Application |
Algorithm |
Evaluation Tool |
Ref. |
|
PUMA: Memristor-Based Accelerator |
General ML Algorithms |
Simulation |
[41] |
|
Memristor-Based FPGA (mrFPGA) |
- |
HSPICE, mrVPR, Xilinx CAD Tools, FPGA |
[11] |
|
Machine Learning |
BCNN |
FPGA |
[4] |
|
Neuromorphic |
MLP, CNN |
Simulation |
[61] |
|
Hyperchaotic System |
Adomian Decompostion |
FPGA |
[62] |
|
Memory Model |
ANN |
Simulation (PSPICE) |
[63] |
|
Neuromorphic |
ANN |
Hardware Realization |
[64] |
|
Intellectual Property (IP) core |
Memrisitive-Chua chaotic |
FPGA |
[65] |
|
Machine Learning |
ANN |
FPGA |
[3] |
|
Memristor-Based Look-up Table (LUT) |
- |
Simulation (LTSPICE IV) |
[66] |
|
Hybird CMOS-Memristor Based FPGA |
- |
TEAM Model |
[67] |
|
Logic Circuit (Adder Circuit) |
- |
FPGA |
[68] |
|
Gate Controlled Memristor |
Single-Layer Perceptron |
FPGA |
[6] |
|
Memristor-Transistor Hybrid FPGA |
- |
Simulation (HSPICE) |
[69] |
|
Multivalued Memristor |
ANN |
FPGA |
[56] |
|
Chaotic System |
Speech Encryption |
FPGA |
[70] |
|
Fractional-Order Memristor |
Grunwald-Letnikov |
FPGA |
[71] |
|
Memristor Hardware (HW) Simulator |
ANN (Testing) |
Quartus II and ModelSim |
[72] |
|
Memristor-Based Chaotic Circuit |
- |
FPGA |
[58] |
Table 1 provides a compilation of research endeavors focused on the implementation or simulation of memristor-based applications tailored for specific algorithms. The table outlines key details, including the nature of the application, the algorithm it is designed to support, the evaluation tool employed for assessment, and the pertinent references for each work. This compilation serves as a resource, facilitating an organized and insightful exploration of the diverse landscape of memristor applications across various algorithmic domains.
Despite the significant advancements in FPGA-based memristor emulation, several challenges and opportunities for future research remain. This section discusses some of these challenges and outlines potential directions for future investigations.
(1) Improving Accuracy: One of the primary challenges in FPGA-based memristor emulation is achieving high accuracy. While existing techniques have shown promising results, further refinement is necessary. Future research could focus on developing advanced modeling approaches that capture the intricacies of memristor behavior more accurately. This might involve considering factors such as non-idealities, variability, and temperature effects to enhance the fidelity of emulation.
(2) Scaling to Large-Scale Systems: Another important challenge is scaling FPGAbased memristor emulation to large-scale systems. As the complexity and size of digital circuits increase, there is a need for efficient techniques that can handle larger designs. Future investigations could explore methodologies to partition and distribute the emulation workload across multiple FPGAs or even across FPGA clusters, enabling the emulation of complex systems while maintaining high performance.
(3) Real-Time Adaptation: The dynamic adaptation approach presented in some studies demonstrates the potential for real-time adjustments to improve emulation performance. However, further research is needed to explore advanced adaptation algorithms and strategies. This could involve leveraging machine learning techniques or feedback control mechanisms to dynamically adapt the emulation parameters based on real-time observations. Such approaches would enhance the adaptability and responsiveness of FPGA-based memristor emulation to varying circuit conditions.
(4) Standardization and Benchmarking: To facilitate comparison and evaluation of different FPGA-based memristor emulation techniques, standardization and benchmarking frameworks are essential. Future research could focus on developing standardized benchmarks and performance metrics that consider various aspects, including accuracy, speed, resource utilization, and power consumption. These benchmarks would enable fair comparisons among different emulation approaches and promote the advancement of the field.
(5) Integration with Design Tools: Smooth integration of FPGA-based memristor emulation with existing design tools is crucial for wider adoption. Future investigations could explore methods to integrate emulation frameworks into popular design flows, enabling designers to validate and optimize memristor-based circuits more effectively. This integration could involve the development of plug-ins, APIs, or dedicated design tool extensions that streamline the emulation process and provide designers with comprehensive analysis and debugging capabilities.
(6) Exploring Novel Applications: While FPGA-based memristor emulation has primarily focused on digital circuit design, there is a vast potential for exploring novel applications. Future research could investigate the use of FPGA-based memristor emulation in areas such as neuromorphic computing, machine learning accelerators, and analog/mixed-signal circuit design. Exploring these applications could lead to breakthroughs in diverse domains and further drive the development of FPGA-based memristor emulation techniques.
In conclusion, this study highlights the current state of FPGA implementation and emulation of memristor devices, identifies key challenges, and outlines potential future directions. The study highlighted various techniques and approaches employed in FPGA-based memristor emulation, ranging from modeling and simulation to hardware implementation and validation. These techniques leverage the flexibility and reconfigurability of FPGAs to emulate the behavior of memristor devices, enabling researchers and designers to study and evaluate memristor-based circuits and systems. Moreover, the study identified several challenges that researchers need to address in future investigations. These challenges, described in detail in Section 4, include scaling to large-scale systems, real-time adaptation, standardization and benchmarking, integration with design tools, and exploring novel applications. Overcoming these challenges will contribute to the advancement of FPGA-based memristor emulation and its wider adoption in diverse domains.
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