Advanced Phase Estimation and Design for Next-Generation Radar Systems: A Digital Approach

In order to meet the needs of high-efficiency and effective phase detection modules for high-rate space-borne systems, block-based phase estimation algorithms integrate fully digitalized phase synchronizers with floating-point arithmetic. The reliability is increased by the synchronized memory architecture and the precise and reliable phase detection network used here. This paper shows a better way to estimate phase that uses a sample block to make the performance trade-offs that come up when estimating phase as the signal frequency changes less noticeable. The aforementioned procedure computes the phase of each succeeding sample point that corresponds to the particular sample block iteratively using FPU-based phase estimation. The proposed idea uses built-in block RAMs in FPGA devices to provide an array-based signal measure analysis methodology. A CORDIC-based post-computation system changes the initial phase, which is directly derived from sample blocks, in a big way for each iteration by using different estimates of the initial phase for each total sample point. The two objectives of this work are both specific and general.

2.1 Related work

According to the review of the literature on phase estimation by millidegree in analog signals of varying nature of time, they are used in various digital circuits like phase locked loop (PLL), finite state machine (FSM), RAM, FIFO, and CORDIC. The various algorithms available for phase estimation aim to optimize the consumption of power, calculate phase differences accurately, and reduce computational operations like adders, modulos, and multipliers [1]. The six equations from (1) to (6) are executed by the blocks, namely, adders, divisions, and multipliers, of the estimating phase [2]. However, these blocks and modules are of fixed point type and are not able to identify the millidegree, i.e., narrow differences in phase. Therefore, by using double precision FPA operations, the speed of estimating by millidegrees will be increased, and it is also due to the fact that adding and multiplying operations are performed without using any propagation of carry [3]. Phase measurement is more commonly used as the building or fundamental block. Normally, PLL is implemented by the use of a binary system of numbers that causes a major delay in propagation [4]. The large part of the delay was due to the high-order phase estimations that contain n numbers of additions and multiplications. Due to this delay, the operation speed of the ADC and the PLL decreased.

If many operators are required for blocks that are used for constant multiplications along with fixed point operations, then a new hypothetical lower limit is executed [5]. Each operation is executed by using pipelining, and the multipliers are constructed with the use of floating point formats. By using this simple structure, pipelined n-input addition and subtraction operations were executed using registers that are used in pipelining [6]. The main drawback of these fixed-point operations of the arithmetic type is that power consumption is very high, and thereby the cost is also very high. However, the one advantage of this fixed point method is that it reduces the PP to increase the speed of the multiplication [7]. The research work of K. H. Chen introduces the linear array multiplier structure by combining the different methods, which is power efficient. But the limitation of this work is that it has more delay and occupies more area. An approach that uses high operation speed and consumes low power was proposed by Chu and Chen. This utilizes the multiplier’s compression tree and spurious power suppression (SPST) for Booth decoders [8]. But it occupies more area, which is the major limitation of this method. Carry Look Ahead adder and ripple carry adder are used for adding the PPs and verifying the multiplier of 32-bit numbers, as proposed by the researcher Hasan K. The authors Dastjerdi and others presented the BZ FAD method of shifting and adding multiplication for implementing the multipliers, which reduced the performance of switching and minimized the utilization of power. The benefit of this approach is that it reduces the cost of computation and increases the speed of operation. The authors Shabbir and others proposed a multiplier based on the Dadda algorithm, which operates at high speed with less power dissipation. Full adders are suggested to make use of the multipliers. Also, with the use of flip-flops, errors in the output of multipliers can be reduced.

From these deliberations, it can be concluded that for detecting the phase of the millidegree in continuous time, the necessary components are Floating Point Arithmetic (FPA) Operations, ADPLL, RAM, and FSM. A few applications of estimating the phase and identifying narrow differences in the phase are multiplication, subtraction, and addition. The number system of residues can identify and correct errors with the help of fault tolerance [9].

The necessity is majorly supported and present in the newest family of FPGAs, Field Programmable Arrays. This family provides an effective platform for implementing the algorithms that are used for detecting the phase. The requirement for this is only a few resources of hardware type and fewer cost blocks of constant multiplication [10].

In the study of Huang et al. [11], the proposed phase estimation in the real-time application and estimated power are 3% using linear programming (LP). The frequency-modulated continuous wave is presented for 4 GHz frequency and a bandwidth of 160 GHz for estimation phase and resolution discussion in the study of Ahmad et al. [12]. When a target's Doppler frequency exceeds half of the chirp repetition frequency, there is Doppler ambiguity in the range-Doppler domain of LFM continuous wave radars. Doppler ambiguity is common in radar systems, so it's important to have a maximum unambiguous Doppler shift extension for a wide range of civil and military radar applications [13]. Several applications that require reliable environmental sensing depend on phased array radar systems. There must be many receiving antenna elements to detect sensitive targets and accurately estimate the direction of arrival (DOA). Digital signal processing is necessarily burdened with a heavy computing load due to the high dimension of the element-level data [14]. When the pulse repetition interval (PRI) is changed on a regular basis, staggered synthetic aperture radar (SAR) can continuously image an extremely wide area while effectively staggered range blind areas. As a result of the changing PRI, azimuth samples are not spread out evenly in a typical staggered SAR. This means that complex resampling processing is needed, including multichannel reconstruction processing and the best linear unbiased (BLU) interpolation [14]. A possible method for the low-cost collection of multiple Doppler weather measurements is multi-static radar. In spite of this, these systems often have much higher two-way side lobe levels than monostatic radars because the receivers use low-directivity antennas. Doppler velocity estimate biases brought on by side lobe contamination have proven to be a major barrier to this technology's wider use [15]. The presented method, based on the frequency-modulated continuous-wave principle, uses both the round-trip phase difference and the frequency difference of the radio wave signal impinging at two widely separated receiving antennas to achieve extremely precise and absolute measurements of the direction of arrival.

In synthetic aperture radar processing, phase unwrapping is a crucial step whose correctness directly affects the dependability of later applications [16]. Many phase unwrapping techniques have been developed, the majority of which require that the phase maintain spatial continuity. However, these assumptions are invalidated by decorrelation noise and aliasing fringes, which cause these techniques to perform poorly [17]. A significant source of interference known as the atmospheric phase screen is introduced by tropospheric propagation delay in multitemporal interferometric synthetic aperture radar (InSAR) applications (APS) [18].

4.1 Amplitude estimation

Here, the input signal is represented as:

$x(t)=A \cos \left(2 \pi f_0 t\right)+\varphi_0$                 (1)

The amplitude, frequency, and phase of the input signal are denoted by A, f₀, and $\varphi_0$, respectively:

$\int_0^T x^2(t) d t=\frac{A^2 T}{2}$                     (2)

In this case, the input signal's single-clock cycle time is represented by T and is equal to 1/f0. The signal energy of one full cycle is calculated as shown below by generating the signal energy equivalent value of the input signal across the single signal period T and across corresponding sample index values of the negative to positive transition np [Nnp].

$\frac{A^2 T}{2} \times \frac{n p\left[N_{n p}\right] T_S}{T}=C S\left[n p\left[N_{n p}\right]\right] T_S$                    (3)

A simplified form of the aforementioned equation is employed to compute the signal amplitude:

$A=\sqrt{\frac{2}{n p\left[N_{n p}\right]}} \sqrt{C S\left[n p\left[N_{n p}\right]\right]}$                        (4)

4.2 Frequency estimation

In this case, the input signal frequency is approximated using Eq. (5) and also by employing a maximum count of zero to positive transitions over a specified sample block as well as related sample points over this interval. To perform these computations, the sampling frequency, which is fixed during the signal processing, is estimated as follows:

$F=\frac{N_{n p}-1}{n p\left[N_{n p}\right]-n p[1]} F_S$                         (5)

The sampling frequency of the ADC is indicated by F_s. The overall samples, in this case, is constant, however, the sample points indexes, as well as their corresponding signal transitions, vary in proportion to the signal frequency, which further causes some inaccuracies while evaluating the phase from the estimated signal frequency. To achieve acceptable system accuracy throughout the phase estimation procedure, it is necessary to derive the precise input signal frequency.

4.3 Single phase estimation

Lastly, via read-write FSM, 2400 samples are recorded in RAM

$\emptyset_c^k=\emptyset_c^{k-1}-\frac{\sum_{m=1}^M\left(\sin \theta_m\left(v[m]-A \cos \theta_m\right)\right)}{A \sum_{m=1}^M\left(\sin \theta_m\right)^2}$                        (6)

where, $\omega=2 \pi f ; \nabla t=\frac{1}{F s}$ and

$\theta m=\omega \times \nabla t \times(m-1)+\varphi_c^{k-1}$

The phase's starting value is corrected and updated by computing the signal phase values of sample points from the input sample block. The advanced version of the phase estimate outcomes ultimately obtained is directly associated with the input signal's solid phase [19].

The hardware algorithm operating on an FPGA initially receives a total of M samples from array.

Furthermore, the substitution mapping function avoids the interaction between the generated vital sequences and the biometric features. This block can be modified to any sequence length throughout the implementation phase for sensor nodes [20].

Block-based phase detection algorithm: Input: s(t); Output: A, F, and P.

(1) From the input high-rate signal sequence, create a signal array of M samples.

(2) The module of BS accepts the input array along with M sample values M 0, 1,...2400 and thereby calculates four parameters, which are as follows: the number of negative to positive transitions (Nnp), the first transition sample index value (np1), and the last transition sample index point (np[Nnp]), before computing the cumulative sum of the squares (CS) for the input array.

(3) Depending on the above four fundamental signal measurements, A as well as F, as represented in Eqs. (4) and (5), are computed.

(4) To calculate millidegrees of phase, the values from Eq. (5) are converted into IEEE 754 double precision format, and Equation is used to calculate the introductory phase (6).

(5) In Eq. (6), an iterative technique is employed to rectify phase errors, and sin and cos values are calculated by employing the CORDIC core to generate finite phase estimates.

The basic module is simulated using a synchronous clock at different stages of the matching process to check the parametric approximation of the synchronized block-based phase detection method and see what happens when the level of accuracy is raised for millidegree phase detection. Typically, in digital systems, the input sinusoidal waveform elements are sampled at a frequency of GHz to produce signal samples. These samples are subsequently converted to binary codes of two's complement and stored in on-chip memory while hardware is being synthesized.

By simulating the effect of increased precision in the phase detection of millidegrees using a synchronized clock in various phases of matching, the estimation made using parameters for synchronizing the phase detection process based on blocks is validated. In the case of a digital implementation, the sinusoidal inputs are formed by sampling signals at a few gigahertz, as seen in Figure 2. Figure 3 illustrates how this data is transformed into the 2's complement form. Using circuitry for synthesizing on-chip memory, it is stored. is used to store it.

Table 1 provides a comparative analysis of the performance of our proposed block-based phase estimator driven by FPA (Floating-Point Arithmetic) with that of existing literature in terms of area, LUT, number of DSP blocks, delay, and power.

2.jpg

Figure 2. Input analog waveform

3.png

Figure 3. Twos complement representation

Table 1. Comparison of the proposed FPA-driven block-based phase estimator's performance with existing literature

Algorithms	Slices (Area)	LUT	DSP Blocks	Delay (ns)	Area*delay	Power (mw)
[23]	23901	21092	20	16.1	3,84,806.1	11.4
[24]	27623	10712	--	15.3	4,22,631.9	9.3
[25]	37612	5011	51	18.2	6,84,538.4	12.12
This work	20941	22371	2	11.29	2,36,423.89	7.2

4.jpg

Figure 4. Hardware utilization

Comparing the proposed FPA-driven block-based phase estimator with existing literature, as shown in Figure 4, it is evident that the new approach exhibits notable advantages in terms of area utilization, LUT, and DSP blocks. However, it is essential to consider the trade-off with delay, as the proposed method shows a higher delay compared to some existing algorithms. The product of area and delay (area*delay) is also significantly influenced by this trade-off. Power consumption, on the other hand, is relatively lower in the proposed work, indicating potential efficiency in power management.

6.1 Energy efficiency

To overcome the drawbacks that are associated with energy, phase detection algorithms that are based on the unified block, as well as suitable clock generation techniques, are included. However, FPU-core-based phase computation requires advanced hardware design compared to the typical phase detection paradigm.

6.2 Internal parallelism

The consecutive path delay data propagation is improved for a specific configuration using the FIFO architecture and a ring counter-facilitated DCO module.

6.3 Parallelization

With the help of the divide as well as conquer technique, the application of hardware can be enhanced. Even though it has been frequently demonstrated that decomposed programmable delay approaches based on buffers generally offer high productivity and versatility to maximize power across models that are evaluated simultaneously.

This study work article introduces a phase detection system that performs at a high level, as well as a frequency synthesizer design that is well optimized for usage in space-based systems. An examination is conducted on the performance indicators in respect to the diverse standard’s needs. Furthermore, the evaluation of phase detection using the FPA for estimating phase with millidegree precision is included in the project. The provided optimized sample block-based estimator model has demonstrated superior performance compared to other existing models for phase detection, making it the ideal choice for FPGA implementation. In conclusion, it is clear that the design of memory models, specifically RAM and FIFO, significantly enhances performance efficiency. Furthermore, a recommended approach for synchronization is proposed after careful research. The testing findings demonstrate that the phase detection strategy being utilized effectively reduces phase error by employing an iterative method to accommodate frequency variations.