Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Gordon Moore, one of the co-founders of Intel Corporation, made a famous prediction in 1965 that came to be known as Moore's Law [1]. He noted that the doubling of transistors on a silicon chip occurred at approximately two-year intervals, resulting in a notable augmentation of computing capabilities. The reduction in feature size has led to several implementation and operational difficulties. It is difficult for CMOS technology to continue to the required level of growth. Since the power consumption of CMOS circuit increases with clock frequency and the frequency determines the computation speed and performance, an increase in performance also increases the power consumption [2]. The challenge is the unsustainable relationship between power consumption versus performance.

The Landauer principles [3, 4] states that the removal of one bit of information during an irreversible computation necessitates a minimum energy dissipation of approximately kT ln(2), where 'k' represents the Boltzmann constant, and 'T' denotes the temperature in Kelvin. This principle implies that for each bit erased, a minimum of kT ln(2) joules of energy must be dissipated in the form of heat. In 1973, Charles H. Bennett published a groundbreaking study titled "Logical Reversibility of Computation," which laid the foundation for the field of reversible computing [5]. Bennett's study [6] explored the theoretical underpinnings and implications of reversible computation, focusing on its fundamental connection to thermodynamics and information theory. In the study, Bennett demonstrated that logical reversibility is a key concept in achieving energy-efficient computation. The concept of reversible computation, which he introduced, involves a scenario in which every computational step is entirely invertible. This feature permits the retrieval of the initial state from the final state with no information loss. Bennett's work showed that reversible computation has significant implications for reducing energy dissipation in computing systems.

Reversible logic, also known as reversible computing or reversible gates, is a computing paradigm that focuses on designing logic circuits or systems that can perform computations without losing information [7]. Unlike conventional logic gates, which are irreversible that discard or overwrite bits, and can result in information loss through dissipative processes like heat generation, reversible logic gates guarantee the individual recovery of all input information from the output, establishing a direct one-to-one relationship between the input and output. This property enables the computation to be reversible, allowing the system to be able to "undo" operations and revert back to the original state. This preservation of information allows for energy conservation since no energy is dissipated as heat due to information loss. The major advantages which one can gain by using reversible logic circuits are:

Energy efficiency: Reversible logic gates are engineered with the goal of reducing energy dissipation [8] while preserving all information throughout computation. As the feature size decreases, power density and leakage currents become more significant challenges. By adopting reversible logic, which inherently aims to conserve energy, it is possible to reduce power consumption and mitigate some of the energy-related challenges associated with scaling [9].

Reduced gate count: Reversible logic gates typically have fewer gates compared to their irreversible counterparts for achieving the same functionality. This reduction in gate count can be advantageous in VLSI chip design, as it helps to minimize the increasing complexity and fabrication challenges caused by shrinking feature sizes. Fewer gates lead to simpler designs, which can enhance manufacturability, yield, and overall circuit performance.

Signal integrity: Reversible logic gates often exhibit lower fan-out and reduced signal propagation delays compared to irreversible gates [10]. These characteristics can help maintain better signal integrity and alleviate some of the challenges related to interconnect delays, crosstalk, and power supply noise. By reducing the impact of signal integrity issues, reversible logic can contribute to more reliable and efficient circuit operation.

Quantum computing considerations: Reversible logic gates have a vital role within the domain of quantum computing [11], which utilizes quantum bits (Qubits) [12-14] that must maintain coherence throughout computation. While reversible logic in classical VLSI chips does not directly address quantum computing challenges, the experience gained from reversible logic design techniques and circuit optimization approaches can be valuable for developing future quantum computing technologies.

Reversible logic along with process technology advancements, device engineering, circuit design methodologies, and manufacturing techniques offers potential benefits in terms of energy efficiency, gate count reduction, and signal integrity. Reversible logic has the potential to drastically reduce power consumption in computing systems, making it a promising approach for energy-efficient computing, especially in scenarios where power consumption is a critical factor, such as in quantum computing, nanotechnology, and low-power embedded systems [15]. Reversible logic gates, such as the Feynman gate, Fredkin gate, Toffoli gate, and Peres gate, Feynman double gate [16-18], have been developed as building blocks for reversible circuits. These gates have the property of being reversible, allowing computations to be performed with guaranteed information preservation. Research in the area of reversible logic encompasses various aspects, including circuit design, synthesis, optimization, fault tolerance, and applications. Researchers continue to explore and develop reversible logic design techniques, algorithms, and architectures to harness its benefits in various applications. Currently, reversible logic is used to implement various combinational and sequential circuits like ALU, counters, encoders, flip flops, fault checkers, etc. [19]. Some research directions and recent advancements in the field are as follows:

Circuit design and synthesis: Researchers are developing efficient methodologies for designing and synthesizing reversible circuits [20-28]. This involves the exploration of novel gate libraries, reversible gates, and building blocks that can perform computations without any loss of information.

Optimization techniques: Several optimization techniques are being explored to lessen the number of gates, garbage outputs, and quantum cost of reversible circuits [29-40]. This includes approaches like gate-level optimization, logic synthesis, gate swapping, and technology mapping.

Quantum reversible logic: Reversible logic plays a significant role in quantum computing [39]. Researchers are investigating reversible logic synthesis techniques tailored for quantum circuits. The objective is to minimize the quantum cost and improve the overall efficiency of quantum computations [41, 42].

Fault-tolerant reversible logic: Fault tolerance is crucial in any computing system. Researchers are studying fault-tolerant designs and fault diagnosis techniques for reversible logic circuits. Redundancy-based approaches, error detection and correction codes, and fault modeling are areas of active research in the area of reversible logic [43-46].

Reversible logic applications: Reversible logic has applications in various fields, including cryptography, image processing, data compression, quantum computing, and low-power computing [47-50]. Research focuses on developing efficient reversible algorithms and architectures for these applications.

Quantum computing and reversible logic: Reversible logic is deeply connected to quantum computing due to the reversible nature of quantum operations [51-56]. Research explores the relationship between reversible logic and quantum computing, including the development of reversible quantum gates and reversible circuit synthesis for quantum algorithms.

Reversible logic and energy efficiency: One of the key motivations behind reversible logic is energy efficiency [57]. Researchers investigate the impact of reversible logic in reducing power consumption, heat dissipation, and overall energy requirements in different computing paradigms, such as classical and quantum computing.

These are just a few research directions within the area of reversible logic. This field draws attention from all disciplines involving aspects of computer science, electrical engineering, quantum physics, and information theory. Ongoing research aims to improve the theoretical foundations, design methodologies, and practical implementation of reversible logic, with the goal of realizing energy-efficient computing systems. In this study, our primary objective is to comprehensively analyze the performance and applications of various reversible logic gates. Specifically, we aim to address the following aspects:

•The quantum cost and gate count associated with different reversible logic gates.

•Real-world applications and implications of these gates, with a particular focus on their relevance in quantum computing, energy-efficient computing, and VLSI chip design.

This paper is structured as follows: Section 2 provides an in-depth analysis of the basic parameters associated with various reversible logic gates. In Section 3, we explore all gates invented till date. Section 4 offers a comparative analysis of our findings and highlights the practical benefits and implications of our research along with its popular applications. Finally, in Section 5, we conclude by summarizing our work and underscoring its novelty and significance.

The methodology for this research paper involves a comprehensive and systematic analysis of various reversible logic gates and their applications mentioned in research papers. The selection of reversible logic gates for analysis was based on several key criteria, including their historical significance, prevalence in modern applications, and representation of different gate types. The chosen gates represent a spectrum of gate functionalities, including Toffoli gates, Fredkin gates, and newer innovations, allowing for a comprehensive analysis of the field. The applications of reversible logic gates were analyzed through a multi-faceted approach. This involved studying their use in quantum computing, energy-efficient computing systems, and VLSI chip design. A comparative analysis was conducted to assess their performance in these domains. Real-world implementations and case studies were also examined to understand the practical implications. The upcoming subsection introduces reversible gates categorized by the dimensions of their inputs and outputs. According to the latest developments in the field, the largest input and output size achievable stands at 6.

3.1 2×2 reversible logic gates

3.1.1 CNOT / FEYNMAN gate

The CNOT gate, short for Controlled-NOT gate [59], is a fundamental reversible logic gate (Figure 2) commonly used in reversible computing and quantum computing. This gate is a 2×2 gate having two inputs clubbed together in the vector form as In={X, Y} and similarly outputs as Out={X, X$\oplus$Y}. It operates on two input bits, a control bit (X) and a target bit (Y), and produces two output bits, maintaining the same control bit and possibly flipping the target bit.

The behavior of the CNOT gate can be summarized as follows:

If the control bit (X) is 0, the output remains the same as the input: (X, Y) → (X, Y).

If the control bit (X) is 1, the target bit (Y) is flipped: (X, Y) → (X, NOT(Y)).

In other words, the CNOT gate copies the value of the control bit to the target bit when the control bit is 1, and leaves the target bit unchanged when the control bit is 0. The CNOT gate is a fundamental component in quantum error correction codes, such as the surface code. The quantum cost is 1. It is used to propagate errors and perform syndrome measurements, allowing the detection and correction of errors that occur during quantum computations. Feynman gate is used for duplication of outputs.

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Figure 2. CNOT gate

3.2 3×3 reversible logic gates

3.2.1 TOFFOLI gate

The Toffoli gate (Figure 3), also known as the Controlled-Controlled-Not (CCNOT) gate, is a fundamental gate in quantum computing. It is named after the physicist Tommaso Toffoli, who first introduced it in 1980. This gate is characterized by 3 inputs and 3 outputs as its 3×3 gate. The inputs are clubbed together to represent in the form of a vector as In={X, Y, Z} and the output as Out={X, Y, XY$\oplus$Z}. The last bit is the target bit, the rest are control bits, when the control bit is 1, the target bit is inverted. The quantum cost is 5. Toffoli gate can be used to realize any function, hence it is known as a universal reversible gate [60]. It is used for quantum error correction applications [61].

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Figure 3. TOFFOLI gate

3.2.2 FREDKIN gate

The Fredkin gate as shown in Figure 4, also known as the Controlled-Swap (CSWAP) gate or the Controlled-Permutation gate, is a reversible three-Qubits gate named after the computer scientist Edward Fredkin who invented it in 1982 [17]. The set of input are In={X, Y, Z} and the outputs are Out={X, XY$\oplus$XZ, X’Z$\oplus$XY}. The input X is mapped directly to the output A. If X=0, Y is mapped to B, Z is mapped to C. If X=1, a swap operation is performed and Y is mapped to C and Z is mapped to B. Therefore, it is also known as a Controlled SWAP gate. The quantum cost is 5. Fredkin gate is used to preserve parity [62].

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Figure 4. FREDKIN gate

3.2.3 PERES gate

The PERES gate (Figure 5), also known as the Peres-Horodecki gate, is a two-qubit gate named after Asher Peres and Michał Horodecki, who contributed to its study in 1996 [16]. It is an entanglement detection gate that determines whether two Qubits are entangled or separable. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, XY$\oplus$Z}. The quantum cost is 4. TRG gate is used for the implementation of a full subtractor. Peres gate can be used to realize functions like NOT, AND, NAND, XOR [61].

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Figure 5. PERES gate

3.2.4 Double Feynman gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, X$\oplus$Z}. The quantum cost is 2. Double Feynman gate shown in Figure 6 is a parity preserving gate [63, 64].

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Figure 6. DOUBLE FEYNMAN gate

3.2.5 BJN gate

In Figure 7, BJN gate is shown. The input is represented as In={X, Y, Z} and the output is expressed as Out={X, Y,(X+Y)$\oplus$Z}. The quantum cost is 5 [62].

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Figure 7. BJN gate

3.2.6 RMUX 1 gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, X’Y+XZ, X’Z+XY'}. The quantum cost is 4. RMUX1 gate as shown in Figure 8 works as a 2:1 MUX, where X is the select line and Y&Z are the two inputs [65].

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Figure 8. RMUX1 gate

3.2.7 TRG gate

The block diagram of TRG gate is shown in Figure 9. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X$\oplus$Y, XY’$\oplus$Z'}. The quantum cost is 4. TRG gate is used for the implementation of a full subtractor circuit [65].

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Figure 9. TRG gate

3.2.8 NEW gate

The block diagram of NEW gate is shown in Figure 10. The input is represented as In={X, Y, Z} and the output is represented as Out={X, XY$\oplus$Z, X’Z’$\oplus$Y’} [65].

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Figure 10. NEW gate

3.2.9 SAM gate

The input vector In={X, Y, Z} and the output vector Out={X’, X’Y$\oplus$XZ’, X’Z$\oplus$XY} for the SAM Gate is shown in Figure 11 [64].

3.2.10 NFT gate

New fault tolerant gate is a gate for parity preserving. Its block diagram is shown in Figure 12. The input is represented as In={X, Y, Z} and the output is represented as Out={X$\oplus$Y, YZ’$\oplus$XZ’, YZ$\oplus$XZ’} [63].

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Figure 11. SAM gate

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Figure 12. NFT gate

3.2.11 RC-I gate

RC-I gate is a single bit comparator circuit. Figure 13 displays its block diagram. The input is represented as In={X, Y, Z} and the output is represented as Out={X, X’Y$\oplus$Z, XY’$\oplus$Z}. It compares X and Y [66].

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Figure 13. RC I gate

3.2.12 UPG gate

Universal programmable gate (UPG) as the name implies can be used to implement logical functions like NAND, AND OR, and NOR. The input is represented as In={X, Y, Z} and the output is represented as Out={X, (X+Y)$\oplus$Z, XY$\oplus$Z}. It can perform logical operations at low quantum cost. Its block diagram is shown in Figure 14 [65].

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Figure 14. UPG Gate

3.2.13. YAG gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, (X$\oplus$Y)$\oplus$(XY$\oplus$Z), XY$\oplus$Z}.

YAG is used to realize AND and OR functions. Its block diagram is shown in Figure 15 [67].

3.2.14 RMUX2 gate

The input is represented as In={X, Y, Z} and the output is represented as Out={X, XYv+XZ, X$\oplus$(Y$\oplus$Z)}. Its quantum cost is 4. In this gate, X is the select line, the gate gives the multiplexed output of Y and Z Its block diagram is shown in Figure 16 [65].

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Figure 15. YAG gate

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Figure 16. RMUX2 gate

3.2.15 HAS gate

Half Adder Subtraction gate has quantum cost 5. The input is represented as In={X,Y,Z} and the output is represented as Out={X, X$\oplus$Y$\oplus$Z, X$\oplus$Y$\oplus$X’$\oplus$Z}. HAS gate is used to implement BCD adder, carry skip BCD adder circuit, half adder, and full subtractor [68]. Its block diagram is shown in Figure 17.

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Figure 17. HAS gate

3.3 4×4 reversible logic gates

3.3.1 Double Peres gate

Double Peres gate is used to implement the full adder [69]. Figure 18 represents its block diagram. The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$X, W$\oplus$X$\oplus$Z, (W$\oplus$X)Z$\oplus$WX$\oplus$Y}. The quantum cost is 6.

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Figure 18. DPG gate

3.3.2 MRG gate

Marrison-Ranganathan gate (MRG) is a programmable gate. The input is represented as In={W, X, Y, Z} and the output is represented as Out ={W, W$\oplus$X, (W$\oplus$X)$\oplus$Y, (WX$\oplus$Z)$\oplus$(W$\oplus$X)$\oplus$Y}. The quantum cost is 6. The 4 operations that MRG gate can perform are OR, NOR, XNOR, and XOR. Its block diagram is shown in Figure 19 [70].

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Figure 19. MRG gate

3.3.3 SAYEM gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W’X$\oplus$WY, W’X$\oplus$WY$\oplus$Z, WX$\oplus$W’Y$\oplus$Z}. The Sayem gate is a versatile component that can be employed in the construction of reversible standard sequential circuits, including popular flip-flop designs such as the T flip-flop and D flip-flop, in conjunction with the Feynman gate. This combination of components allows for the creation of advanced sequential logic circuits with the unique property of reversibility. Its block diagram is shown in Figure 20 [60].

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Figure 20. SAYME gate

3.3.4 TSG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W’Y$\oplus$X’, (W’Y$\oplus$X’)$\oplus$Z, (W’Y$\oplus$X’)Z$\oplus$WX$\oplus$Y}. The TSG gate, in conjunction with the CNOT (Controlled-NOT) gate, serves as the fundamental building block for the implementation of a full adder. This powerful combination of gates enables the creation of a full adder circuit, a fundamental component in digital arithmetic. Its block diagram is shown in Figure 21 [71].

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Figure 21. TSG gate

3.3.5 DKG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W’Y+WZ’, (W$\oplus$X)(Y$\oplus$Z)$\oplus$YZ, X$\oplus$Y$\oplus$Z}. DKG gates can singly work as either a full adder or a full subtractor. W is the control line, if W is set to 0, it will work as full adder, and if W is set to 1, it will work as full subtractor. Its block diagram is shown in Figure 22 [71, 72].

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Figure 22. DKG gate

3.3.6 SCL gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, X, Y, W(X+Y)$\oplus$Z}. SCL gate is used to add 6 to the sum for correcting it to get the actual BCD sum. Its block diagram is shown in Figure 23 [69].

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Figure 23. SCL gate

3.3.7 BVF gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$X, Y, Y$\oplus$Z}. BVF is a double XOR gate. The BVF gate serves the purpose of extracting essential inputs to fulfill the fan-out requirements. Its block diagram is shown in Figure 24 [73].

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Figure 24. BVF gate

3.3.8 ALG gate

The input is represented as In={W,X,Y,Z} and the output is represented as Out={W, W$\oplus$X$\oplus$Y, (W$\oplus$X)Y$\oplus$(WX$\oplus$Z), (W’$\oplus$X)Y$\oplus$(W’X$\oplus$Z)}. The ALG gate can perform multiple operations like full adder, full subtractor, XOR, NAND, and NOR. Its block diagram is shown in Figure 25 [71].

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Figure 25. ALG gate

3.3.9 PPHCG gate

Parity Preserving Hamming Code Generator (PPHCG) gate preseves parity. The input is represented as In={W, X, Y, Z} and the output is represented as Out={X$\oplus$Y$\oplus$Z, W$\oplus$X$\oplus$Y, W$\oplus$X$\oplus$Z, W$\oplus$Y$\oplus$Z}. The quantum cost is 6. A PPHCG is used to ensure fault tolerance in Hamming error coding and detection circuits by preserving the input data's parity, enhancing the accuracy and reliability of error detection and correction. Its block diagram is shown in Figure 26 [63].

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Figure 26. PPHCG gate

3.3.10 IG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W$\oplus$X, WX$\oplus$Y, XZ$\oplus$X’(W$\oplus$Z)} IG gate can be used to perform to perform logical operations like inverter, EX-OR, AND, EX-NOR and OR. It is a one- through gate which means one of the input variables is also the output. Its block diagram is shown in Figure 27 [74].

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Figure 27. IG gate

3.3.11 MKG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, Y, (W’Z’$\oplus$X’)$\oplus$Y, (W’Z’$\oplus$X’)Y$\oplus$(WX$\oplus$Z)}. MKG gate is used to realize logical functions like NAND, NOT, NOR, EX-OR, AND, EX-NOR and OR. The MKG gate is categorized as a two-through gate, indicating that it has the distinct property of utilizing two of its input variables as outputs as well. Its block diagram is shown in Figure 28 [74].

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Figure 28. MKG gate

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Figure 29. BME gate

3.3.12 BME gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, WX$\oplus$Y, WZ$\oplus$Y, W’X$\oplus$Y$\oplus$Z}. The quantum cost is 5. Its block diagram is shown in Figure 29 [68].

3.3.13 PTR gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={(X$\oplus$Y)’, X$\oplus$Y$\oplus$Z, Z(X$\oplus$Y)+XY, X’(Y$\oplus$Z)=YZ}. Its block diagram is shown in Figure 30 [75].

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Figure 30. PTR gate

3.3.14 PAO gate

The Peres And-Or Gate (PAOG) represents an extension of the Peres gate, specifically designed for ALU (Arithmetic Logic Unit) implementation. The input is expressed as In={V,W,X,Y,Z} and the output is expressed as Out={W, W$\oplus$X, WX$\oplus$Y, ((W$\oplus$X)$\oplus$Z)$\oplus$(WX$\oplus$Y)}. The PAOG can be configured with two select inputs, allowing it to execute four unique logical operations on its two output signals. These operations encompass OR, NOR, AND, and NAND. This versatile gate has a quantum cost of 6, and its block diagram is visually represented in Figure 31 [65].

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Figure 31. PAOG gate

3.3.15 RC gate

The input vector of reversible comparator gate is In={W, X, Y, Z} and the output is represented as Out={W, W$\oplus$WX$\oplus$Y, X$\oplus$Y$\oplus$WX, W$\oplus$X$\oplus$Z}.The quantum cost is 5. Y and Z are the control lines when =0 and Z=1, it will compare W and X. Its block diagram is shown in Figure 32 [65].

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Figure 32. RC gate

3.3.16 RC-II gate

RC-II gate is a reversible sign bit comparator. The input vector of Reversible comparator gate is In={W, X, Y, Z} and the output is represented as Out={W, W’X$\oplus$Z, W$\oplus$X$\oplus$Y, WX’$\oplus$Z}. RC-II gate is used to compare two unsigned bits. Its block diagram is shown in Figure 33 [66].

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Figure 33. RC-II gate

3.3.17 HNG gate

The input is represented as In={W, X, Y, Z} and the output is represented as Out={W, X, W$\oplus$X$\oplus$Y, (W$\oplus$X)Y$\oplus$(WX$\oplus$Z)}. The quantum cost of the HNG is 6. When Z=0, the circuit works as full adder. Its block diagram is shown in Figure 34 [65].

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Figure 34. HNG gate

3.3.18 HCG gate

As outlined by James et al. [76], the Hamming Code Generating gate operates as a pass-through gate, wherein one of the input variables is simply mirrored as the output. Its block diagram is shown in Figure 35. The input is represented as In={W, X, Y, Z} and the output is represented as Out={X, W$\oplus$X$\oplus$Y, W$\oplus$X$\oplus$Z, W$\oplus$Y$\oplus$Z}. HCG is used to implement Hamming error coding and detection circuits [75].

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Figure 35. HCG gate

3.3.19 FAS gate

The Full Adder Subtraction (FAS) gate is capable of executing both full addition and full subtraction operations. The input is represented as In={W, X, Y, Z} and the output is represented as Out={W$\oplus$X$\oplus$Y, (X$\oplus$Y$\oplus$Z)W$\oplus$(Y$\oplus$Z)X, Y, X$\oplus$Y$\oplus$Z}. Its quantum cost is 8. Its block diagram is shown in Figure 36 [75].

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Figure 36. FAS gate

3.4 5×5 reversible logic gates

3.4.1 PPRG gate

Parity preserving reversible gate is the one through which means one of its inputs is also an output. It is a universal gate. The input is characterised as In={V, W, X, Y, Z} and the output is characterised as Out={V, (V’X’$\oplus$W’)$\oplus$Y, (V’X’$\oplus$W’)Y$\oplus$VW$\oplus$X, VW’$\oplus$X’$\oplus$(V’X’$\oplus$W’)’Y, (Y$\oplus$Z)$\oplus$VX}. P2RG gates can be singly used to build a full adder and full subtractor. Its block diagram is shown in Figure 37 [77].

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Figure 37. PPRG gate

3.4.2 MG gate

Morrison gate is programmable reversible logic gate. The input is represented as In={V, W, X, Y, Z} and the output is represented as Out={V, V$\oplus$W, (V$\oplus$W)$\oplus$X,VW$\oplus$Y, ((V$\oplus$W)$\oplus$Z)$\oplus$(VW$\oplus$Y)}. The quantum cost of the MG is 7. Its block diagram is shown in Figure 38 [65].

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Figure 38. MG gate

3.4.3 OD gate

The input is enumerated as In={V, W, X, Y, Z}, while the output is enumerated by Out={(W+X)$\oplus$Y$\oplus$V, W, X, Y, (W+X)Y$\oplus$Z$\oplus$VY}. Overflow Detection gate has a quantum cost of 10. OD gate is used for overflow detection. Its block diagram is shown in Figure 39 [75].

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Figure 39. OD gate

3.4.4 NG-PP

The input is characterised as In={V, W, X, Y, Z} and the output is characterised as Out={V, W, X, V$\oplus$W$\oplus$X$\oplus$Y, V$\oplus$W$\oplus$X$\oplus$Z}. The NG-PP gate incurs a quantum cost of 5, as reported by Misra et al. [78]. It is used as a parity generator and parity checker circuit [79]. Its block diagram is shown in Figure 40.

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Figure 40. NG-PP gate

3.4.5 HG-PP gate

The input is described as In={V, W, X, Y, Z} and the output is described as Out={V$\oplus$X$\oplus$Z, W$\oplus$X, X, Y$\oplus$Z, Z}. The quantum cost of the HG-PP gate is 4. The number of 1’s in input and output are the same. HG-PP gate is used to design the hamming code [78, 80]. Its block diagram is shown in Figure 41 [75].

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Figure 41. HG-PP gate

3.5 6×6 reversible logic gates

3.5.1 BSCL gate

As per Rashmi et al. [81], the Binary Coded Decimal Subtraction Correction (BSCL) gate has a dual role. It can either compute correction logic for BCD subtraction or, based on the control signal, transmit the data directly to the output.The input is represented as In={U, V, W, X, Y, Z} and the output represented as Out={Z$\oplus$Y, Z’U+Z[Y’{U$\oplus$(V+W)}+Y{U+VWX}], Z’V+[Y(V$\oplus$W)+Y(V$\oplus$WX)], Z’W+ZY’W+ZY(W$\oplus$X), Z$\oplus$X, Z}. In this context, the control signal Z dictates the output behavior: when Z equals 0; U, V, W, X, and Y are directly transmitted to the output. However, if Z equals 1 and Y is 0, the output reflects the nine's complement of the input binary number represented by U, V, W, and X. Alternatively, if Y equals 1, the output results from adding the binary number 0001 to UVWX, providing a valid corrected subtraction outcome. Its block diagram is shown in Figure 42 [75].

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Figure 42. BSCL gate