Hardware-in-the-Loop Simulation and FPGA Implementation of a Single-Phase PFC Controller

Electrical systems and equipment draw power from the utility grid, and Power Factor (PF) is a key measure of how efficiently this power is utilized. When PF drops below acceptable levels (e.g., below 0.92), a significant amount of power is converted into harmonics, which is reflected back into the utility grid, causing harmonic distortion [1]. The rapid adoption of Electric Vehicles (EVs), smart appliances, telecom equipment, and renewable energy sources such as fuel cells, solar photovoltaic, and wind energy are exacerbating this issue. This rising integration of renewable energy sources, coupled with the growing complexity of modern power systems, has posed significant challenges to maintaining high power quality. As a result, maintaining power quality at the utility grid is becoming a challenge for utility companies [2].

To address these challenges, IEEE standards have been established to regulate harmonic distortion and ensure improved PF across all devices connected to the utility grid [3, 4]. In this work, a Power Factor Correction (PFC) control system is developed to enhance PF, improve power quality, and reduce the strain on electrical distribution networks. The proposed solution is developed on Field-Programmable Gate Array (FPGA) platform due to its unique advantages, such as high speed, parallel processing capability, re-programmability, and re-configurability. These features make FPGAs ideal for implementing real-time control systems. The FPGA-based hardware design offers design flexibility, low latency, and the potential to develop Application Specific Integrated Circuits (ASICs). This approach provides a cost-effective and efficient solution that can be readily used as a pre-stage for appliances and electrical systems connected directly to the utility grid. The proposed system not only enhances energy efficiency and lowers electricity costs but also mitigates the risks of equipment instability and failure, while increasing the load-handling capacity of existing electrical infrastructure [5].

In the development of control strategy, testing is a critical step that enables thorough validation of functionality, stability, reliability, and performance of the control system. Recently, the Hardware-in-the-Loop (HIL) simulation has emerged as a powerful technique for closed-loop validation of control strategies prior to physical prototyping of any system. By enabling real-time investigation of control systems, HIL simulation protects physical systems from potential damage during the early design phases. Additionally, it reduces development costs, accelerates design timelines, and shortens time-to-market, making it a widely adopted approach in the design, development, and testing of industrial systems and various other applications [6-11].

1.1 Motivation

The increasing integration of renewable energy sources, rapid adoption of EVs, and the growing use of smart appliances have significantly increased the complexity of modern power systems, posing challenges to maintaining high power quality and grid stability. PF is critical in improving energy efficiency and mitigating harmonic distortion, which, if unaddressed, can lead to grid instability, equipment failures, and increased operational costs. However, the development and validation of PFC systems require robust, real-time testing platforms to ensure performance and reliability. FPGA-based HIL simulation offers an ideal solution, enabling precise, real-time evaluation of PFC systems while reducing development costs, minimizing risks, and accelerating design timelines. By leveraging the speed, parallelism, and re-programmability of FPGAs, this study addresses the need for efficient and reliable PFC units that enhance power quality and support the evolving demands of modern power systems. Also, ASIC can be developed as PFC is recommended front-end for all utility grid connected equipment.

1.2 Literature review

PFC units can be implemented using various topologies, broadly classified as active and passive PFC topologies [12]. Passive PFC topologies are primarily used in low-power (approximately 100 W) and cost-sensitive applications, employ low-pass filters and capacitor banks [13, 14]. However, active PFC topologies are widely adopted due to their superior performance. Active PFC circuit utilizes high frequency switching devices to synchronize the current phase with the input voltage, shaping the current wave closer to a sine wave. This improves the PF and reduces harmonic distortion [12, 15]. The commonly used PFC topology is the conventional boost topology, that includes a front-end full-bridge rectifier (diode) followed by a boost converter. This method is well-suited for applications in the low to medium power range. At high power levels, diode bridge plays a crucial role in the application, necessitating effective management of heat dissipation within a confined surface area [16, 17]. Recently, many bridgeless topologies were also used in high-power applications. These bridgeless PFC circuits lower the conduction loss by minimizing the semiconductor component count in the current path, thereby enhancing efficiency [18-20]. Though they result in better efficiency, their operating range is limited. Also, these topologies can work well at high load conditions (60%-100% load) but fail at light load conditions. Some bridgeless topologies use auxiliary circuits with simple control schemes along with the conventional converter, to improve efficiency at light load conditions [21-23]. In this research, a versatile bridgeless active boost converter topology is adopted to support PF correction and harmonic compensation, offering improved efficiency.

Further, in the literature, various types of current controllers have been discussed for active filtering applications. The synchronous reference frame-based current controller is widely used due to its popularity in various applications; but it has limited bandwidth and requires extensive transformation computations [24]. Input voltage-based current reference control methods are another common choice but often suffer from harmonic distortion, requiring modifications or hybrid control schemes [25, 26]. The hysteresis current controller is simple to implement but operates with a variable switching frequency. Although modified hysteresis methods achieve constant switching frequency, they are complex and less suitable for fully digital implementations.

The Dead-Beat Current Control (DBCC) technique, a digital control method, is widely adopted in power converter applications such as active rectifiers, power filters, and Pulse Width Modulation (PWM) rectifiers [27]. DBCC offers constant switching frequency, high control bandwidth, and straightforward digital implementation, making it an ideal choice for this work. While alternative controllers like Predictive Current Control (PCC) and Sliding Mode Control (SMC) are also effective for PFC applications, PCC demands intensive computation that challenges real-time FPGA execution, whereas SMC often introduces chattering that increases EMI and can interfere with soft-switching in resonant stages. In contrast, DBCC ensures fast dynamic tracking with minimal computational burden, deterministic FPGA implementation, and negligible disturbance to the resonant stage, making it the most practical and effective choice for the proposed system. Digital controllers for PFC systems can be implemented on various hardware platforms, including FPGAs, DSPs, microcontrollers and microprocessors [28-31]. Microprocessors and microcontrollers are popular for their accessibility, low cost, and ease of use. However, these platforms execute control functions sequentially, leading to low computational speeds [32]. DSPs, optimized for mathematical computations, demand substantial processing power and a robust system architecture to manage complex control systems. Additionally, since DSPs rely on software-based execution, they are less suited for high-speed control algorithms requiring rapid response. FPGAs, in contrast, offer quick response time, parallel architecture, high speed, and re-programmable and re-configurable capabilities, making them ideal for fast and reliable implementations [33-35].

Despite their advantages, FPGAs have yet to gain widespread acceptance in power electronics control applications. This is primarily due to key limitations, including the high cost of firmware development, the need for specialized HDL programming expertise, and the relatively higher cost of FPGA boards compared to other control platforms. Additionally, the complexity of HDL programming presents a significant challenge in developing fully digital control systems for power converter applications. Designing discrete-time equations and implementing them onto an FPGA platform remains a bottleneck for researchers and developers in this domain.

Now, for controller validation, HIL simulation has emerged as an efficient and versatile approach that supports mixed-system simulation and real-time performance evaluation. The literature highlights various HIL simulation environments, such as MATLAB-Modelsim, MATLAB-Simulink-XSG (Xilinx System Generator), MATLAB-Simulink-DSP Builder, Opal-RT, dSPACE, e-Tap, Typhoon HIL, Plexim RT Box, NI HIL, and Speedgoat HIL [8, 36-38]. Many of these platforms are proprietary and expensive, making them suitable for large-scale or high-power applications such as automotive systems, aerospace systems, and other industrial systems where physical system verification is costly or hazardous for the operator. Other HIL platforms integrate MATLAB with DSPs, microprocessors, FPGAs, or custom platforms for the development of applications like power filters, photovoltaic systems, distributed generators, delta inverters etc. In all these applications, HIL platforms are used for development, testing, and performance evaluation of systems in closed-loop environments. 

Despite extensive research on HIL approaches, the application of FPGA-based HIL simulation for single-phase PFC systems remains underexplored. Furthermore, the potential for leveraging FPGA's parallel processing capabilities to achieve real-time accuracy and implementation flexibility in PFC control needs further investigation. To address these gaps, in this work, a HIL simulation test-bench is developed using MATLAB-Simulink-XSG software integrated with Xilinx VIVADO Design Suite. This setup facilitates closed-loop testing and hardware implementation of the control system on a reconfigurable FPGA platform [33, 39-41]. All system blocks are discretized, and their discrete-time equations are implemented on the FPGA, allowing evaluation of the controller’s tracking and transient performance under dynamic operating conditions. This approach ensures efficient and accurate validation of the complete digital controller for a DC-DC converter with a front-end PFC stage, a configuration widely recommended for all utility grid-connected systems, and also supports future ASIC development.

The core novelty of this work lies in the unified FPGA-based implementation of a single-phase PF correction controller integrated with a resonant inverter-based DC–DC converter. Unlike prior studies [33, 42], which primarily focused on HIL validation platforms, this work extends the concept to a fully functional FPGA realization that simultaneously executes both the Dead-beat current control (for the PFC stage) and hybrid control of the DC–DC converter on a single digital platform. Discrete-time control equations for both stages are formulated and implemented, enabling seamless coordination and real-time execution within FPGA constraints. This integrated architecture enhances hardware efficiency, reduces controller redundancy, and provides a direct pathway toward ASIC development. Furthermore, while [33] primarily employs HIL-based validation for an Induction heating system, which has linear load characteristics, the present work validates a controller for a system with non-linear load behavior. In addition, it advances the approach by combining HIL-based verification with experimental validation of the integrated architecture on an FPGA platform, thereby demonstrating both feasibility and reliability in practical operation.

This paper is organized as follows: The power converter system for single-phase PFC is covered in Section 2. Design of control system considering resonant load is covered in Section 3. Section 4 covers simulation results with different parametric conditions as well as the experimental results, followed by conclusions in Section 5.

The PFC boost converter receives grid voltage and proportionally generates the DC bus voltage for the connected resonant converter system (DC-DC converter). Here, input current wave-shape is always maintained sinusoidal, in phase with input grid voltage and DC bus voltage is regulated simultaneously using an efficient PFC control strategy. Further, in converter systems, the resonant tank (L_S - C_S - C_P) between the modulation and rectification stage provides the resonant inverter with an inherent input-output gain that depends on the excitation frequency and PWM duty ratio. By controlling these two parameters, the system effectively regulates both output voltage and load current, as they influence the rectifier’s input under varying load conditions. An efficient resonant converter control strategy enables simultaneous adjustment of the PWM duty cycle and switching frequency in response to load variations. Accordingly, the main functions of the proposed controller are: (i) To maintain input PF near unity, (ii) To regulate DC bus voltage at set reference value, (iii) To regulate output voltage, and (iv) To maintain Zero Voltage Switching (ZVS) of the resonant converter at all load conditions. These functions are achieved using FPGA controller, consisting of two major control blocks: PFC control unit and resonant converter control unit. The controller generates control pulses for both the front-end active rectifier (AC-DC converter) and resonant converter respectively, concerning the received feedback signals, as shown in Figure 2. Here, based on the received input and feedback signals, the PFC control unit continuously modifies the switching control pulses (G1−G4) and ensures that the input PF is always maintained close to unity and the output DC bus voltage is regulated to the set reference voltage level, even though the electrical grid source voltage fluctuates. Similarly, the load parameters are continuously sensed by FPGA controller, and appropriate switching control pulses (G5-G8) are generated and supplied to the LCC resonant converter such that the load current and terminal voltage are always controlled as per the custom load specifications, with respect to the present load. By using the high-speed and accurate control capabilities of FPGA technology, the combined functionality of these control units ensures efficient and reliable operation of the power converter system. This not only enhances power quality and adaptability to load changes but also improves overall energy efficiency, making the system suitable for diverse power electronics applications.

Figure 2. Controller block diagram

Figure 3. Block diagram of single-phase PFC control unit

A block diagram of discrete-time PFC control unit is shown in Figure 3. Here, a Phase Locked Loop (PLL) block continuously tracks the input grid voltage (Vgrid) and generates frequency-feedback reference signal ($\omega$) for the implementation of current controllers in the grid connected systems. The synchronous reference frame based PLL is preferred in this design, because it handles grid disturbances, harmonics and noise effectively over other PLL implementation methods. Further, it aligns directly to the fundamental frequency component of even the distorted grid signal and also performs better in the presence of unbalanced conditions. Here, first the quadrature filter generates the stationary frame quadrature components ($\alpha$ and $\beta$) of input Vgrid. This quadrature filter is basically cascade of two low-pass filters that introduces total phase shift of $90^{\circ}$. The discrete-time equation of single stage filter is as given in Eq. (1):

$y(n)=y(n-1)+\frac{\omega \cdot T_s}{2}[x(n)+x(n-1)]$     (1)

Here, $T_S$ represents discrete-time system's sampling time, $n$ denotes the present time step and $\omega$ is the angular frequency. These quadrature components of Vgrid ($\alpha-\beta-0$ signals) need to be converted into rotating reference frame ($d-q-0$), for which $\alpha-\beta-0$ to $d-q-0$ transformation is carried out using Park transformation as in Eq (2):

$\left[\begin{array}{l}u_d \\ u_q \\ u_0\end{array}\right]=\left[\begin{array}{ccc}\cos \theta & \sin \theta & 0 \\ -\sin \theta & \cos \theta & 0 \\ 0 & 0 & 1\end{array}\right] \cdot\left[\begin{array}{c}v_\alpha \\ v_\beta \\ v_0\end{array}\right]$      (2)

Figure 4. Flowchart - Phase tracking loop in PLL

In this equation, $v_\alpha, v_\beta$ and $v_0$ are stationary frame components, $\theta$ is estimated phase angle, $u_d$, $u_q$ and $u_0$ are rotating frame components of the grid voltage. This transformation requires sinusoidal signals with instantaneous phase angle ($\theta$), which is fed back from the PLL block, to ensure that loop remains locked to the input grid signal. The $q$-axis component of this transformation ($u_q$), directly represents the phase error. If value of $u_q=0$, means the input grid signal (Vgrid) and the estimated PLL output are perfectly synchronized. Otherwise, the PLL iteratively refines its output ($\omega$) to minimize the phase error. The PI controller-1 processes this $u_q$ signal and accordingly modifies the estimated frequency ($\omega$), ensuring that it remains locked to the grid voltage's frequency and phase. The flowchart (Figure 4) illustrates the phase tracking loop within the PLL used in the Dead-Beat PFC controller - a fully digital process that synchronizes the control system with the grid voltage during every control interrupt. The loop begins with the measurement of grid voltage, which are first transformed into the stationary $\alpha-\beta$ frame and then into the rotating $d-q$ frame using the previously estimated phase angle ($\theta$) from the last sampling period. The resulting $q$-axis voltage ($u_q$) serves as the phase error signal; any nonzero value indicates phase misalignment. This error is processed by a PI controller that generates a frequency correction term ($\Delta \omega$), which is added to the nominal grid frequency. The corrected frequency ($\omega$) is then integrated to produce an updated and synchronized phase angle ($\theta$) for the next sampling step. The updated $\theta$ is fed back into the Park transformation for the next iteration and simultaneously supplied to the DBCC block. This ensures that the $d$ - $q$ transformations and voltage/current reference calculations remain precisely aligned with the grid, enabling accurate and fast PF correction.

Overall, the entire current control loop remains synchronized with the grid through this PLL mechanism, ensuring that the input current is always in phase with the grid voltage - a fundamental objective of PFC. The loop operates continuously, adaptively adjusting both $\omega$ and $\theta$ to maintain phase lock and provide a stable, real-time reference for the DBCC controller.

For generation of the sinusoidal signals ($\sin \theta$ and $\cos \theta$) required in Park transformation, Harmonic Oscillator (HO) block is used. The discrete-time equations of HO, obtained using Hybrid discretization method are,

$x(n+1)=x(n)+h . y(n)$      (3)

$y(n+1)=y(n)-$ h. $x(n+1)$     (4)

In these equations, consider initial conditions as $x(0)=0$ and $y(0)=1$. The constant $h$ is defined as $h=\omega \cdot T s=2 \pi f T s$, where $f$ is the desired oscillation frequency, and $T_S$ represents time interval of discrete-time samples. The frequency of sinusoidal outputs (i.e. $x(n+1)$ and $y(n+1)$) is decided by a constant $h$. Its implementation is carried out in a similar manner as discussed in the study [42].

The PLL block's output, $\theta$ is fed back as an input to this HO block. Accordingly, it generates the required frequency $\sin \theta$ and $\cos \theta$ signals that are used in the above stationery to rotating reference frame transformation. In all, the reference frame $d-q-0$ rotates at an angular speed of $\omega$, where $\omega=2 \pi f, f$ is the fundamental frequency of the input grid voltage and iteratively locks the PLL output to the grid voltage. Now to regulate the DC-bus voltage, the measured bus voltage (Vdc) is compared with set reference voltage (Vdcref) and an error signal (Ve) is generated. This error is processed by the voltage PI controller (PI controller-2), which generates the reference current (i$_{invref}$) used to shape the input current. The $z$-domain representation of PI controller is given in Eq. (5):

$H(z)=K_P+\frac{K_i \cdot T_S}{2} \frac{(Z+1)}{(Z-1)}$     (5)

This PI controller’s discrete-time equation is obtained using bilinear transformation and given as,

$i_{\text {invref}}(n)=i_{\text {invref }}(n-1)+\left(K_P+\frac{K_i T_S}{2}\right) V_e(n)+\left(\frac{K_i T_S}{2}-K_P\right) V_e(n-1)$      (6)

In this equation, $K_P$ and $K_i$ represent proportional and integral gains, $T_S$ is sampling time, $V_e$(n) is voltage error and i$_{invref}$ is the final output of the PI controller-2. Here, the proportional and integral gains ($K_p$ and $K_i$) of the PI controllers were determined using MATLAB's System Identification Toolbox and PID Tuner. For the PFC control unit, the open-loop system behavior was first analyzed in the simulation domain, and input-output data were collected. Mainly, for the PLL loop (PI Controller-1), the relationship between frequency error and phase angle was evaluated, while for the DC bus regulation loop (PI Controller-2), the duty ratio versus DC bus voltage characteristics were obtained. These datasets were processed using the System Identification Toolbox to derive the estimated transfer function models of both plants. The identified models were then supplied to MATLAB's PID Tuner, which computed optimal $K_p$ and $K_i$ values by shaping the closedloop frequency response to achieve the desired gain and phase margins. The obtained gains were subsequently validated and fine-tuned in the simulation domain and then used for FPGA implementation.

These outputs of the voltage PI controller and PLL block along with other inputs received are processed by an efficient DBCC block. A digital DBCC technique is chosen here because of its advantages, including constant switching frequency, higher control bandwidth suited for active rectifiers, fast dynamic response, high accuracy and ease of digital implementation. This DBCC scheme achieves PF correction by ensuring that the current drawn from input grid is always synchronized with the grid voltage. To achieve this, first the reference current waveform is generated, which is in phase with the input grid voltage and its amplitude is proportional to the connected load power demands. Then the actual grid current is measured and compared with the reference current, and an error signal is calculated. This error signal is further used to compute the reference control signal for the PWM modulator. The generalized discrete-time equation of DBCC is given in Eq. (7). These discrete-time Eqs. (6) to (8) are derived in detail in Appendix.

$\begin{gathered}V_{\text {ref}}(n)=-V_{\text {ref}}(n-1)+2 \cdot V_{\text {grid}}(n)+K_1\left(i_{\text {invref}}(n)-i_{\text {inv }}(n-1)\right) \\ +K_2\left(i_{\text {invref}}(n)+i_{\text {inv}}(n-1)\right)\end{gathered}$     (7)

Here, V$_{grid}$ is input grid voltage, i$_{invref}$ is output of the PI controller, i$_{inv}$ is converter current, K₁ and K₂ are functions of input LCL filter inductance and PI gains. The stability and bandwidth of the proposed DBCC are determined by the placement of closed-loop poles in the z-domain, which is controlled through the coefficients K₁ and K₂ derived from the converter’s discrete-time model. Above DBCC equation relates the present control action to past and present current and voltage samples, enabling a one-step-ahead prediction of the required reference voltage. For stable operation, the closed-loop poles must lie within the unit circle, and this can be achieved by tuning K₁ and K₂ according to the converter dynamics and sampling period. In the ideal dead-beat case, the closed-loop pole is located at the origin, resulting in one-sample current tracking and the highest achievable loop bandwidth, theoretically approaching the Nyquist frequency. Increasing $K_p$ (through K₁) shifts the pole toward the negative real axis, thereby increasing damping and enhancing transient robustness, whereas increasing K_i (through K₂) moves the pole toward the positive real axis, which reduces steady-state error but simultaneously decreases damping and narrows the bandwidth. Proper tuning of these gains ensures a fast dynamic response, minimal steady-state error, and a robust current loop for stable operation under varying grid and load conditions. Detailed pole-placement derivations and numerical analysis have been provided in the Appendix section.

The DBCC processes all these feedback, reference and input signals to generate a final reference signal, V$_{ref}$ for the PWM modulator. The Sine-Triangle modulator block accordingly generates the exact control pulses (G1-G4) for the front-end active rectifier (AC-DC converter), to force the converter current to match the reference current in next 1 or 2 grid cycles and regulate DC bus voltage. Thus, the converter current is always in phase with input grid voltage and the DC bus voltage is also regulated. In all, the PF as well as DC bus voltage is regulated by this PFC control unit.

To regulate the DC-DC converter output voltage (V$_{out}$), the controller has to dynamically change the PWM duty ratio. Here, if the switching frequency remains unchanged then the ZVS is lost. Therefore, real-time tracking of the resonant frequency and corresponding duty ratio regulation are essential. These objectives are achieved by modifying PWM based on output voltage demand while simultaneously adjusting the converter's switching frequency to maintain soft switching conditions. To fulfil these requirements, a control strategy is designed comprising of two primary loops: resonant frequency tracking and output voltage regulation. The resonant frequency tracking loop includes a phase shifter and attenuator stage, a comparator, and an integrator block, as detailed in the study [33]. In this method, the load current io(t) is sampled and passed through the phase shifter and attenuator block to produce an output signal V$_{psa}$(t). The corresponding discrete-time equation is formulated using the Euler’s explicit integration method and is presented in Eq. (8).

$V_{p s a}(n)=K_A\left(V_{p s a}(n-1)+\frac{T_s}{\tau}\left[i_0(n)-V_{p s a}(n-1)\right]\right)$     (8)

Here, n is the current time step, K_A is an attenuation factor and τ is a time constant. This τ is a function of IGBT’s output capacitance, switching frequency and peak load current. The output ($V_{p s a}$) is further compared with load current, and a square wave is generated. This square wave has frequency, same as load current, but it always leads the load current and thus ensures ZVS of the resonant converter. The integrator stage processes this square wave and generates a ramp signal for the preceding PWM modulator block. Dynamic slope compensation logic discussed in the study [33] is implemented here to improve the performance of the resonant converter system.

In designing the voltage control loop, the output voltage (V$_{out}$) is initially measured and compared with a reference voltage (V$_{ref}$), generating an error signal ($V_e$). This voltage error is then processed and corrected using a discrete-time PI controller to maintain the desired output. Gains of the PI controller are tuned accordingly, using PID tuning methods discussed in the study [33] to achieve a required control action. Further, the PI output modifies the phase shift duty ratio of resonant converter using a PWM modulator block. The output from the PI controller is continuously compared with a ramp signal generated by the frequency tracking loop within the PWM modulator block. This comparison produces phase-shifted control pulses (G5-G8), which are then used to drive the corresponding switches (Q5-Q8) of LCC resonant converter.

Implementing entire control architecture on FPGA platform is challenging and time consuming, requiring skilled programming. Further, as the control complexity grows, even the experienced programmers face difficulties. To overcome these challenges, this work uses XSG, a model-based design technique, to generate HDL code for FPGA deployment. This approach offers several key benefits: (i) it facilitates rapid prototyping of control systems on FPGA, thereby reducing development cycles and accelerating time-to-market; (ii) it offers an integrated environment for both simulation and real-time testing on a single platform; (iii) simplifies design using XSG even for developers with basic HDL knowledge.

The implementation of DBCC controller using XSG blocks is depicted in Figure 5. In the same manner, quadrature filter, αβ-dq0 transformation, PI-controller and all other blocks of resonant converter control unit (Figure 2) are implemented using XSG block sets. In the overall design various logical, arithmetic, relational, DSP, control, mathematical operations, registers etc. are used. Here, MCode block is programmed so that the generated V$_{ref}$ signal remains in the acceptable limits. For declaring user defined sample rates in delay and register blocks, the Assert blocks are used. To convert Boolean output into fixed-point data required by arithmetic blocks, cast block is used. Gateway-in and Gateway-out blocks are used to interface Simulink blocks with XSG blocks.

Figure 5. Dead-beat current control using XSG block sets

The proposed PF correction control system has been developed and validated on reconfigurable FPGA board for the resonant inverter-based DC-DC converter application. This approach integrates both, PF correction and DC-DC converter control on a single digital platform (Zynq-XC7Z020-1clg484 FPGA), eliminating the need for two separate controllers, and thereby enhancing the reliability of the controller hardware. HIL simulation result shows that the DBCC technique has effectively maintained the input PF close to unity and regulated the DC bus voltage even in the fluctuating source conditions. Moreover, stable output voltage is maintained during dynamic load and voltage variations with fast transient recovery and minimal steady-state error. Timing and power analysis for implementation on Zynq board observed a total power dissipation of 0.307 W, with a worst negative slack of 2.1 ns, hold slack of 0.073 ns, and pulse width slack of 3.3 ns. These results ensure that the FPGA can be operated at an increased speed whereas the resource utilization table ensures that the practical system can be implemented using low-cost FPGA boards. This HIL simulation platform enables rapid prototyping and efficient hardware implementation of the controller on FPGA, thereby significantly reducing the overall time required for control strategy design and testing. The experimental results are comparable with the HIL simulation results; this demonstrates the effectiveness and reliability of the proposed control strategy. Moreover, this approach–featuring control strategy with inbuilt PF correction mechanism can be readily used with minor modifications, for identical DC-DC converter applications such as EV/Hybrid EV charging, telecom rectifiers, server power supply, and photovoltaic systems.

Future work will focus on extending the proposed controller to multi-phase and three-phase PFC systems for higher power levels, implementing the design in a custom ASIC or SoC to enhance integration and efficiency, and validating the approach through full-scale hardware testing to demonstrate its scalability for industrial applications.