Ahmed Aziz Elwehili*
| Dalenda Ben Aissa
© 2025 The authors. This article is published by IIETA and is licensed under the CC BY 4.0 license (http://creativecommons.org/licenses/by/4.0/).
OPEN ACCESS
While design automation plays a crucial role in contemporary large-scale digital systems, the automation of the transistor-level circuit design process continues to pose significant challenges. Recent studies indicate that deep learning algorithms may be utilized to determine optimal transistor dimensions in compact circuitry, such as voltage-controlled oscillators. However, achieving robust and efficient analog circuit design automation in integrated circuit field remains challenging. A deep neural network architecture is introduced for the automatic sizing of analog circuit components, specifically targeting radio frequency applications within the 2 to 5-GHz range. A novel deep learning model designed to simulate voltage-controlled oscillators for microwave applications. This work introduces four algorithms: DNN, CNN, RNN, and SCINet. Two characteristics have been evaluated: output power and phase noise. The models achieved an accuracy of 96%-97% and exhibited a loss ranging from 0.0024 to 0.0036. The prediction of the required features demonstrates outstanding performance across all utilized models. We aim to determine the most effective deep learning model suitable for a specific dataset and computational setting.
voltage-controlled oscillator, deep learning, convolutional neural network (CNN), sample convolution and interaction network (SCINet), recurrent neural network (RNN), deep neural network (DNN)
Deep learning has garnered increasing attention in various emerging sectors, including computer aided design (CAD) and integrated circuit design. Electronic circuits are based on analog signals, which are transformed, processed, amplified, measured, and displayed by analog circuits. However, many circuit characteristics need to be changed while designing analog ICs. It must rely on numerous simulations because the relationship between parameters and performance is nuanced and occasionally unclear from mathematical computations [1].
A crucial component of phase locked loop PLL that determines the PLL's power consumption and spatial occupancy is a CMOS voltage-controlled oscillator (VCO). A vital part of many RF transceivers, VCOs are frequently linked to signal processing functions such as frequency selection and signal creation. Today's RF transceivers use PLLs to achieve the customizable carrier frequencies that they need. These PLLs incorporate a feedback loop with a less precise RF oscillator whose frequency is controllable by a control signal. Because they provide periodic signals used in digital circuits for timing and frequency conversion in RF circuits, VCOs are essential components of communication systems. They depend on a control input, often a voltage, to determine their output frequency. A circuit whose output frequency is a linear function of its control voltage is an ideal voltage-controlled voltage oscillator. For the majority of applications, the oscillator had to be tunable, meaning that its output frequency had to be dependent on a control input, often a voltage [2, 3].
The effectiveness of electronic circuits and design approach is inherently connected to the growing demand for improved energy efficiency in engineering systems. The efficacy of electronic circuit and design process is intrinsically linked to the growing demand for enhanced energy efficiency in engineering systems. The production of electronic circuits, such as analog circuit, is a demanding endeavor that necessitates much time and effort from circuit designers. It necessitates considerable human expertise and encompasses multiple labor-intensive phases. The designer uses the circuit simulator repeatedly during the circuit parameter optimization process to achieve an optimal design. To achieve high-performance optimal designs, it is essential to reduce the time and effort expended by circuit designers in the design process. Furthermore, to attain high-performance optimal designs, it is essential to reduce the workload on circuit’s designers and accelerate the design process of the circuits. Proposals for methodologies in simulation based optimization for analog circuit design have been made. Sequential Bayesian Optimization (SBO) entails the incorporation of an optimization agent into the interaction loop between experts and simulator [4, 5].
The expert-agent-simulator loop has been created using several optimization techniques, including simulated annealing, genetic algorithms, and particle swarm optimization. The expert-agent-simulator loop has been developed with several optimization techniques, such as genetic algorithm, simulated annealing, and particle swarm optimization [6, 7].
Time series data refers to a sequential collection of results from a process, measured or seen at specified intervals. The objective of a dataset is to document data and actions pertinent to its subject matter. The primary task in time series applications is to identify underlying patterns in previous data, with an emphasis on forecasting future states or data. Time series forecasting (TSF) is extensively utilized in predicting the stock market, weather forecasting, traffic congestion anticipation, and various other domains.
Decision-makers get the ability to recognize and reduce risks and support well-informed decision-making through forecasting. Particularly, deep learning models provide encouraging outcomes after achieving remarkable success in computer vision and natural language processing. For TSF problems, each model offers a possible remedy. With some frameworks, multi-objective and multi-granularity prediction and multi-modal TSF have been performed [8].
In this work, deep learning models have been proposed for the simulation of a microwave VCO. Two features were predicted which are output power and phase noise. Four algorithms have been introduced in this work, deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), and sample convolution and interaction network (SCINet).
This paper has been organized as follows: the related work is presented in section two. The work preliminaries are explained in section three. Section four shows the description of the deep learning models used in this work. In section five, the system design has been proposed. The results and their discussion are presented in section six. Finally, section seven shows the conclusion and suggestions for future work.
Chen [1] employs a RNN to enhance parameter sizing in circuit design. Following a brief training period of 15 minutes, the RNN demonstrates the ability to predict essential parameters such as gain, bandwidth, power, and frequency, thereby accelerating critical design decision-making. The algorithm's reliability and applicability were validated through the prediction of parameters for integrated operational amplifiers and VCOs. The research introduces augmented neural networks (AugNN) formulated to simulate the behavior of steady state oscillator in the temporal domain. This study introduces a multi-output AugNN that integrates a gradient scheme and a training mechanism tailored for multi-phase oscillators. The AugNN presents a novel methodology for modeling VCOs through the utilization of RNNs to accurately represent nonlinear dynamic current-voltage interactions. The model functions as a black box, is safeguarded by intellectual property rights, and exhibits efficacy in time-domain analysis. 4 This paper introduces the MODE-CNN optimization framework, which combines the Multi-Objective Differential Evolution method with CNN surrogate models. The method reduces resource use in simulations while maintaining precision. The framework utilizes Latin Hypercube Sampling and Quantile Transformation to enhance predictive accuracy, in conjunction with CNN surrogate models for evaluating circuit performance. The framework exhibits enhanced performance relative to traditional methods in optimization outcomes, confirming its effectiveness in analog ICs. Tang et al. [9] examined the utilization of machine learning methods for voltage management in distribution networks that include electric vehicles and dispersed power sources. The system integrates electronic on-load tap changers and line voltage regulators inside an operational feeder comprising 9 solar systems, 2 charging stations, and 41 substations. Hourly measurements and irradiation data are employed to build a DNN for accurate tap position predictions. Musiqi et al. [10] utilized shallow neural networks (SNNs) to limit learning to one component size at a time, enabling the usage of little training dataset set and managing component interdependencies.
The approach has been confirmed across three categories of RF microcircuits, yielding predictions that are within 5% of actual values and achieving responses in under 5 seconds. The approach is efficient and can be utilized for various analog circuit configurations [11].
This paper introduces an optimization framework for analog circuit design that leverages machine-learning techniques to identify the ideal device sizes for enhanced performance. The approach employs machine learning models alongside spice simulations to inform the optimization algorithm, leading to quicker convergence and fewer spice calls. Multi-layer perceptron and random forest (RF) regression are utilized to predict circuit specification, whereas multilayer perceptron classifiers are employed to predict saturation conditions in transistors. The framework has been validated through three circuit topologies, and the results indicate improved optimum values along with reduced standard deviations [12].
VCOs have been utilized in the creation of clock frequencies during transmission and receiving. The produced clock signal can be utilized in digital, analog, or hybrid circuits. Various solutions have been devised to diminish the power consumption of oscillators and enhance tuning efficiency. In contemporary power ICs, on-chip integrated VCO circuits often produce clock signals to modify switching power supply. In a VCO, the clock frequency is regulated by a tuning voltage. VCO circuits are classified into ring VCO circuits and LC-VCO circuits. This work examines the LC VCO.
3.1 LC VCO topologies
The CMOS cross-coupled structure is used by several LC VCO topologies to supply the negative resistance. Three distinct LC VCO architectures have been examined in this paper. Performance metrics have been taken into account, including power, area, phase noise, tuning range, and central frequency. NMOS LC VCO, PMOS LC VCO, and NMOS PMOS LC VCO are the three general categories into which LC VCO can be divided. Figure 1(a)-(b) and Figure 2(a)-(b) display the LC VCOs that were analyzed. Every architecture has unique benefits and drawbacks, therefore the VCO tuning range is a design consideration for the designer. 1/√2πLC, where L is the inductance and C is the tank's total capacitance, provides the center frequency of an LC VCO. The necessary LC tank is formed using a varactor. Essentially, a varactor is a variable capacitor that can have its capacitance altered by varying the voltage differential between its two plates. The inductor typically determines the LC tank's quality factor, and the quality factor for inductance is directly proportional to its inductance. However, when a designer attempts to raise the inductance, two main effects occur. First, the design's area grows significantly, and second, the inductor's parasitic capacitance restricts the varactor's capacitance and, consequently, the range of capacitance that may be varied. The varactor's capacity to be tuned decreases as the parasitic capacitance increases [13].
Figure 1. (a) NMOS VCO; (b) NMOS VCO with footer
Figure 2. (a) PMOS VCO; (b) PMOS VCO with header
3.2 The benchmark dataset
A series of systematically recorded observations arranged in chronological order is essential for the formulation and validation of a time series model. The model to be developed must effectively characterize the relationship between data points within a specified dataset. A VCO produces a periodic signal whose frequency can be adjusted over a broad spectrum, ruled by a voltage input value. The cross-coupled VCO has emerged as a widely adopted configuration for achieving sustainable oscillation because of its power consumption and low phase noise [14]. Figure 3 illustrates the characteristics of the dataset.
Figure 3. VCO dataset features
This section will examine advanced deep learning architectures for TSF. Each of these deep learning algorithms has unique benefits and appropriateness for TSF. Selecting the suitable model is contingent upon the data attributes, the problem's complexity, and the performance criteria [15]. Moreover, proficient hyperparameter optimization and data pretreatment are essential for attaining precise forecasts. This section will present an overview of models categorized as DNN, CNN, RNN, and SCINet.
4.1 Deep neural network
A DNN is a neural network including two or more hidden layers. Deep learning models mostly consist in multilayer perceptron (MLP) and feedforward neural networks with two or more hidden layers. Every deep learning algorithm starts with DNN models. The several hidden layers help the DNN models to understand the complex characteristics in the large dataset. This feature helps the DNN to efficiently manage extremely dynamic and nonlinear data. Several DNN models have been lately presented [16].
4.2 RNN-based model
RNNs are a specialized neural network architecture designed for the analysis of sequential data, such as time series and natural language text. Unlike traditional feedforward neural networks, RNNs possess recurrent connections that facilitate the transfer and preservation of information over time. The core principle of RNN entails employing the output from the prior time step as the input for the present time step. This establishes connections among sequential data, enables RNNs to handle sequences of differing durations, and captures temporal linkages and contextual nuances within the sequences [17]. The hidden state in RNN serves as the memory element within the network at each time step. At each time step, the concealed state is revised and subsequently conveyed to the subsequent layer or time step of the network. RNNs employ a memory propagation mechanism to save information from prior data, enabling them to apply that information to adjust current outputs. Figure 4 depicts the internal architecture of a conventional recurrent neural network. The graph indicates that x(t) represents the input vector to the neurons at a time t, and h(t) denotes the hidden vector at that same time t. The conventional RNN neuron is structured to receive the preceding hidden state h(t)-1 in conjunction with the current input x(t). The essential component of an RNN is its unit, which possesses an internal memory state that retains prior knowledge. The equation employed to determine the internal concealed state of a RNN [18].
4.3 SCINet
SCINet employs an encoder-decoder framework. The encoder operates as a hierarchical convolutional network, skilled in capturing dynamic temporal dependencies across different resolutions, employing a wide range of convolutional filters. The SCI-Block shown in Figure 5(a) functions as the core element of the SCINet. It divides the input features F into two sub-features, Fodd and Feven, using splitting and interactive learning mechanisms. The splitting divides the original features F into two sub-sequences, Feven and Fodd, by differentiating between the odd and even elements. This leads to a less refined temporal resolution, yet it preserves most of the information from the original sequence. The SCINet is organized hierarchically by several SCI-Blocks, leading to a tree-structured framework.
At the i-th level, there exist 2l SCI-Blocks, where l varies from 1 to L, with L denoting the total number of levels as shown in Figure 5(b). In the k-th stacked SCINet, the input series X (k = 1) or the feature vector ˆXk−1=ˆXk−11,…,ˆXk−1τ (k>1) experiences a systematic downsampling process and is analyzed by SCI-Blocks at multiple levels, enabling efficient feature learning across diverse temporal resolutions. The data collected from the earlier stages will be systematically compiled, indicating that the attributes of the deeper stages will integrate more nuanced temporal details communicated from the shallower stages. This method enables the effective capture of short and long terms temporal dependencies presented in the time series sequence data. The data collected provides a foundation for future studies and potential applications in the field. It is essential to analyze the results thoroughly to draw meaningful conclusions. When there are sufficient samples of training dataset, it could stack K layers of SCINets to obtain much better prediction accuracy as shown in Figure 5(c), but with more complex model structure [19, 20].
Figure 4. RNN architecture
Figure 5. SCINet block diagram [19]
Figure 6. CNN applied to TSF [21]
4.4 CNN
CNNs [22] illustrated in Figure 2, possess a complex architecture that typically encompasses convolution, pooling, and fully connected layers. CNNs are characterized by three primary attributes: local connectivity, shared weights, and translation equivariance. Local connectivity is characterized by the exclusive connection of each neuron in a CNN to its specific input region, known as the receptive field. Furthermore, the neurons in a particular layer employ an identical weight matrix. Translation equivariance refers to the capability of CNNs to identify specific patterns, irrespective of their location within the input image. The application of 1D convolution (refer to Figure 6) to an input sequence X = [x1, …, xL] using a specified kernel w of size q is articulated as follows [21]:
y(t)=(w×X)(t)=∑q2a=−q2w(a)X(t−a)∀t∈[1,…,L]
where, X represents the input sequence, y is the output sequence, w is the model weights. It is crucial to recognize that in the autoregressive approach, the kernel size q correlates with the model order, which is usually established through model selection methods like cross-validation [23]. Additionally, CNN can stack multiple convolutional layers, transforming the input data (such as historical time series values) into a more suitable higher-level representation for the forecasting task.
The VCO utilizes a symmetrical cross-coupled configuration, as depicted in Figure 7. This configuration is frequently employed in VCOs, enabling an output swing that nearly reaches rail-to-rail levels. The cross-coupled pMOS–nMOS configuration is critical for minimizing 1/f noise [24]. Table 1 displays the design variables of the different designs criterion, including the ranges of values considered. The source input and inductance values were established prior to each case and utilized as inputs for the design of sizing process, while Vtune was adjusted in each design to achieve the necessary tuning range. A VCO produces a periodic signal with a tunable frequency over a broad spectrum, based on a voltage input. The cross-coupled VCO is commonly utilized for sustainable oscillation owing to its low phase noise and reduced power consumption.
Figure 7. VCO
Table 1. VCO design values
|
Variable |
Minimum- Value |
Maximum-Value |
|
Oscillation-frequency (GHz) |
2.0223 |
9.92 |
|
Tuning-range (MHz) |
52.44 |
724.4 |
|
Phase-noise (db/Hz) |
-101.7 |
-88.2 |
|
Power-consumption (mW) |
1.386 |
3.33 |
|
TransistorQ1 length (µm) |
0.5 |
4.1 |
|
TransistorQ1 width (µm) |
2.5 |
55 |
|
TransistorQ2 length (µm) |
0.5 |
4.4 |
|
TransistorQ2 width (µm) |
3 |
55 |
|
TransistorQ3 length (µm) |
0.8 |
4.2 |
|
TransistorQ3 width (µm) |
15 |
98 |
Figure 8 illustrates the comprehensive workflow framework that has been proposed. The process starts with obtaining a dataset of parameters that meet the size constraints, utilizing VCO features as input for various deep learning models. This work proposes three types of training algorithms: DNN, RNN, CNN, and SCINet. We explore the fundamental architectures for processing an input dataset and provide a thorough evaluation of the latest advancements in deep learning prediction models. Various models are likely tailored to meet distinct design objectives. We rigorously analyze the performance of these models using the same time series input dataset on an identical hardware computing system. The observed performance may indicate the design adaptability across all the ranked models achieved or the predetermined number of iterations has been completed. This section offers an in-depth analysis of the development and implementation of the CNN model, along with enhancements in the optimization process. We input performance metrics into the model and allow it to predict the design parameters. The codebase includes a comprehensive model training and evaluation pipeline, illustrated in Figure 7. This facilitates a seamless integration of the machine learning process with the analog circuit process. In the training phase, we adhere to the conventional machine learning process to import data and develop the model. Given the varying ranges of performance metrics and parameters targeted by the models, we initiate the process by applying preprocessing to normalize the data within the range of [-1, 1]. The training data is divided by randomly selecting 60% of the data points for the training dataset, 20% for the test dataset, and 10% for the validation dataset. The neural networks are trained for 100 epochs utilizing the Adam optimizer, set at a learning rate of 0.001.
Figure 8. Conventional procedure of VCO
DNN, RNN, CNN, and SCINet are the four distinct algorithms that were utilized in the process of training and evaluating the proposed system when it was applied to the VCO dataset. The results of the tests conducted on the various deep learning algorithms are presented in Table 2. The accuracy and loss are the most important performance metrics which represents how the model is trained well or may be overfitting learning. These metrics are evaluated in two phase first, while training, in this phase a validating datasets is required which in this work chosen to be 10% from the total dataset. Secondly, the model is tested on a test dataset (unseen dataset 30% of the total dataset) to check the final model performance which should be close to those of the training metrics.
Table 2. Testing hyperparameter of the proposed models
|
Model |
Accuracy |
Loss |
Precision |
Recall |
|
SCINet |
0.96819 |
0.0036 |
1.0 |
0.3603 |
|
DNN |
0.9755 |
0.0027 |
1.0 |
0.3754 |
|
RNN |
0.9723 |
0.0024 |
1.0 |
0.3661 |
|
CNN |
0.9709 |
0.003 |
1.0 |
0.3675 |
Figure 9 illustrates the accuracy and loss of training by demonstrating that the SCINet method demonstrates superior training performance, even though other algorithms also provide strong performance. As can be seen in Figure 10, the SCINet algorithm is the one that produces the most accurate prediction for output power when compared to other algorithms. As can be seen in Figure 11, the prediction of phase noise is displayed, and SCINet also displays the best results. Figure 12 shows a combination of the different prediction models together, as a result of the results that were acquired, it is possible to observe that the forecast is nearly identical to the initial characteristics that are displayed in Figure 3.
Figure 9. Different deep learning models accuracy and loss
Figure 10. Output power prediction
Figure 11. Phase noise prediction
Figre 12. Comparison of prediction of different deep learning models
Through the examination of time series data, TSF is a powerful instrument that not only offers decision-making techniques but also provides predictive insights. It also extends across a wide range of applications. During this research, we suggested an alternative deep learning model for simulating VCOs for microwave applications. In the course of this work, four different algorithms—namely, DNN, CNN, RNN, and SCINet—have been presented. Output power and phase noise are the two characteristics that have been examined and evaluated. After training, the models achieved an accuracy of 96%-97% and a loss that ranged from 0.0024 to 0.0036. Additionally, the prediction of the necessary characteristics demonstrates an outstanding performance across all of the models that were utilized. Our objective is to determine which deep learning model is the most suitable for a certain dataset and the computational environment that is available. Our research findings indicate that SCINet outperforms other deep learning models in terms of accuracy, loss, precision, and recall. While our testing configuration may not demonstrate that SCINet excels among all timeseries applications, it exemplifies a meticulously designed model that warrants comprehension of its architectural framework. Integrating analog circuit simulations with machine learning predictions directs the genetic algorithm towards optimal solutions. It is essential to ensure that the transistors operate within the required region for the proper functioning of analog circuits. In preparing for future projects, it is essential to evaluate multiple datasets and to simulate various VCO architectures.
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