S.Seenuvasamurthi* | G. Nagarajan
OPEN ACCESS
Low noise, low power, minimum delay and smaller area are the prime factors in the current VLSI system design. There are many sources for noises that exhibit various types of noise. Noise in digital ICs can be credited to various sources such as PSN due to circuit switching transition, deviations in device parameters due to process changes, crosstalk noise caused by capacitive coupling among neighbouring circuit interconnects, noise due to charge sharing and charge leakage. Reducing noise is an important factor in VLSI design. This work involves the analysis and reduction of switching noise in the inverter based equivalent circuit model in 45 nm technology. Also, aims to minimize the power utilization, area and delay. Further the noise analysis is extended to half adder circuit and ALU. The noise value observed for the proposed circuit is 140 μV whereas it is 33 mV for the existing circuit. The same circuit is implemented in GDI based half adder and 4 bit ALU. The simulation result show that the proposed model has reported low noise compared with the existing methods
ALU, gate diffusion input (GDI), simultaneous switching noise (SSN)
ALU-Arithmetic Logic Unit
BM-Binary Multiplier
CMOS-Complementary Metal Oxide Semiconductor
CPU-Central Processing Unit
EDA-Electronic Design Automation
GDI-Gate Diffusion Input
IC-Integrated Circuit
PSN-Power Supply Noise
PTL-Pass Transistor Logic
RCA-Ripple Carry Adder
SoC-System on Chip
SSN-Simultaneous Switching Noise
VDSM-Very Deep Sub Micrometer
VLSI-Very Large Scale Integration
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