Design of FPGA-based Handwriting Image Recognition System

Design of FPGA-based Handwriting Image Recognition System

Lei Wang Ziheng YangGuangqiang Xu Meili Fu Yu Wang

Information and Network Center, Heilongjiang University, Harbin 150080, China

School of Electronic Engineering, Heilongjiang University, Harbin 150080, China

Corresponding Author Email: 
yzh@hlju.edu.cn
Page: 
426-437
|
DOI: 
https://doi.org/10.18280/ama_b.600212
Received: 
12 May 2017
| |
Accepted: 
25 May 2017
| | Citation

OPEN ACCESS

Abstract: 

This paper designs a program to realize the handwriting image recognition algorithm using FPGA. The digital character recognition system designed in this paper is composed of software design and hardware design. In terms of software, the character processing is divided into image denoising, image binaryzation, grey processing and refinement treatment. Each process algorithm is developed with Matlab. By virtue of its powerful image processing function, the algorithm is simulated. By transforming the DBN into large data volume matrix operations and combining the implementability of FPGA, each link of the identification algorithm is determined. The program mainly uses Altera Cyclone IV chip and several calculation cores connected by DBN are realized through hardware programming. The hardware implementation of the module function and algorithm is verified through Modelsim simulation of each module.

Keywords: 

Handwriting image recognition, FPGA, DBN, Matrix multiplication

1. Introduction
2. DBN Recognition Algorithm
3. Realization of FPGA
4. Conclusions
  References

[1] M.S.B. Ameur, A. Sakly, A. Mtibaa, Implementation of real coded genetic algorithms using FPGA technology, 2013, 10th International Multi-Conference on Systems, Signals and Devices (SSD). 

[2] M.S.B. Ameur, A. Sakly, A. Mtibaa, Implementation of real coded PSO algorithms using FPGA technology, 2014, 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA).

[3] M.S.B. Ameur, A. Sakly, FPGA based hardware implementation of bat algorithm, 2017, Applied Soft Computing, vol. 58, pp. 378-387.

[4] D. Bratton, T. Blackwell, Understanding particle swarms through simplification: a study of recombinant PSO, 2014, Proceedings of the 9th 1013 Annual Conference on Genetic and, Evolutionary Computation (GECCO’07). pp. 2621–2627.

[5] M.C. Chi, Self-adaptive check and repair operator-based particle swarm optimization for the multidimensional knapsack problem, 2015, Applied Soft Computing, vol. 26, pp. 378–389.

[6] Q. Wanga, Y. Lia, B. Shaob, S. Deya, P. Lia, Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA, 2017, Neurocomputing, vol. 221, pp. 146–158.

[7] M.F. Tolba, A.M. Abdelaty, N.S. Soliman, L.A. Said, A.H. Madian, A.T. Azar, A.G. Radwan, Y. Lia, FPGA implementation of two fractional order chaotic systems, 2017, Int. J. Electron. Commun, vol. 78, pp. 162–172.

[8] W. Ni, X. Gao, Y. Wang, Single satellite image dehazing via linear intensity transformation and local property analysis, 2017, Neurocomputing, vol. 176, pp. 25–29.

[9] J.L. Raheja, S. Subramaniyam, A. Chaudhary, Real-time hand gesture recognition in FPGA, 2016, Optik, vol. 127, pp. 9719–9726.

[10] J.L. Raheja, A. Singhal, Sadab, A. Chaudhary, Android based portable hand sign recognition system, recent trends in hand gesture recognition, 2015, Science Gate Publishing, USA, pp. 1–18.

[11] D.V. Rao, S. Patil, N.A. Babu, N. Muthukumar, Implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages, 2006, Int. J. Theor. Appl. Comp, vol. 1, no. 1, pp. 9–34.

[12] J. Li, H. Zhang, D. Yuan, M. Sun, Single image dehazing using the change of detail prior, 2015, Neurocomputing, vol. 156, pp. 1–11. 

[13] P. Irgens, C. Bader, T. Lé, D. Saxena, C. Ababei, An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm, 2017, Hardware X, no.1, pp. 68–75.

[14] B. Schrauwen, M. D’Haene, D. Verstraeten, J.V. Campenhout, Compact hardware liquid state machines on FPGA for real-time speech recognition, 2008, Neural Networks, vol. 21 pp. 511–523.

[15] K.F.C. Yiua, Z.B. Li, S.Y. Low, S. Nordholm, FPGA multi-filter system for speech enhancement via multi-criteria optimization, 2014, Applied Soft Computing, vol. 21, pp. 533–541.