A Hybrid-Controlled Dual-Input DC-DC Converter for Multi-Source Energy Systems

3.1 Circuit configuration

A single inductor is used in the proposed DISO converter, with its essential specifications summarized below:

Input Sources:

V1 = 14.3 V is the primary source (e.g., battery or primary DC bus);

V2 = 5.0 V is the auxiliary source (e.g., PV / USB / harvesting input).

Power Stage Elements:

Single inductor: L = 180 µH (ferrite core, low DC resistance (DCR))

Output capacitor: C = 22 mF with equivalent series resistance (ESR) ≈ 5 mΩ (low-ESR polymer)

Input selection switches: S₁, S₂ (GaN FETs, R_on ≈ 0.3 mΩ)

Mode control switch: S₃ (GaN FET, R_on ≈ 0.3 mΩ)

Diodes: D₁, D₂ (Schottky SiC, V_f ≈ 0.3 V)

3.2 Operating mode analysis

The converter is capable of selecting one of three operating modes depending upon the real-time correlation between input and output voltages. Mode selection occurs seamlessly without human intervention and uses hysteresis logic to prevent rapid, repetitive switching (chattering) during threshold crossings.

Table 2(a) summarizes the illustrative voltage conditions, duty-cycle ranges, and source-switching states for buck, boost, and buck–boost operation, while Table 2(b) details the corresponding device states, diode conduction intervals, and principal current paths in each operating mode.

Control Parameters:

TDM scheduling period: T = 250 µs (4 kHz).

Nominal power-share ratio: α = 0.70 to V1 [14].

Load conditions: 3.5 Ω → 1.8 Ω step at t = 5 ms. Figure 1 presents the circuit schematic of the proposed converter.

Figure 1. Circuit schematic of the proposed dual-input single-output (DISO) DC-DC converter

The switch timing for each operating mode is summarized in Table 3.

5.1 Model predictive control implementation

The hybrid control strategy is structured around the MPC algorithm as a supervisory layer. At each stage, it selects the duty cycle by solving a finite-horizon optimization problem, ensuring efficient response to varying conditions [7, 10, 11].

Algorithm Structure:

1. Candidate Origination: The algorithm is tested for 11 discrete duty cycle values spanning

d ∈ [0.25, 0.75] at uniform intervals of Δd = 0.05.

2. State Prediction for Each Candidate:

${{x}_{pred}}\left[ i \right]=x\left[ k \right]+{{T}_{s}}\cdot \left( A\cdot x\left[ k \right]+B\cdot {{d}_{i}} \right)$                    (13)

Notation Explanation:

${{x}_{pred}}\left[ i \right]$ = Predicted state for candidate duty cycle i.

${{d}_{i}}$ = Candidate duty cycle (one of 11 values from 0.25 to 0.75).

$i$ = Candidate index (i = 1, 2, ..., 11).

3. Cost Evaluation: Calculate quadratic cost function:

$J\left[ i \right]={{w}_{v}}\cdot {{({{V}_{ref}}-{{v}_{C,pred}}\left[ i \right])}^{2}}+{{w}_{d}}\cdot {{({{d}_{i}}-0.5)}^{2}}$                     (14)

The 0.5-centered duty penalty acts as a soft regularizer to avoid control-effort saturation; it does not shift the operating point, which is set by the outer voltage loop.

Notation Explanation:

$J\left[ i \right]$ = Cost function for candidate i (having penalty value)

${{w}_{v}}$ = Voltage error weight (for better voltage regulation)

${{V}_{ref}}$ = Reference voltage (6.7 V setpoint)

${{v}_{C,pred}}\left[ i \right]$ = Predicted capacitor voltage for candidate i

${{w}_{d}}$ = Duty cycle penalty weight (to avoid excessive control effort)

${{({{d}_{i}}-0.5)}^{2}}$ = Penalty considered for deviating from 50% duty cycle

Optimal Duty Cycle Selection:

${{d}^{\text{*}}}\left[ k \right]=arg\underset{{{d}_{i}}}{\mathop{min}}\,J\left[ i \right]$                    (15)

For choosing the duty cycle candidate that gives the lowest cost i.e. best performance.

Mode-Dependent Weighting Values:

Buck mode: ${{w}_{v}}=3000$ (moderate weighting).

Buck-Boost mode: ${{w}_{v}}=3500$ (higher weighting for stability).

Boost mode: ${{w}_{v}}=4000$ (maximum weighting for critical regulation).

Duty penalty: ${{w}_{d}}=1\times {{10}^{-4}}$ (small penalty).

Performance Analysis:

The MPC implementation offers distinct benefits:

Constraint handling through candidate limitation.

Optimal transient response through predictive optimization.

Variable weighting for the Mode-aware adaptation.

Discrete evaluation for Computational efficiency.

Figure 4 illustrates the MPC cost-function surface as a function of duty cycle. Figure 5 presents the histogram of MPC duty-cycle selections and the cost-function evolution during load transients.

Figure 4. Model predictive control (MPC) cost-function surface versus duty cycle, indicating the cost-minimizing optimal duty

Figure 5. Histogram of model predictive control (MPC) duty-cycle selections and cost-function evolution during load transients

5.2 Fuzzy logic control design

The FLC subsystem effectively handles system nonlinearities and improves disturbance rejection through fuzzy membership functions and rule-based adaptation [12, 13].

Error Classifications:

$\text{if}\left| \text{e} \right|<{{\text{e}}_{\text{thr}}}\text{then }\!\!~\!\!\text{ }{{\text{e}}_{\text{class}}}=0\text{(Zero)}$

$\text{else }\!\!~\!\!\text{ if }\!\!~\!\!\text{ e}<-{{\text{e}}_{\text{thr}}}\text{then}{{\text{e}}_{\text{class}}}=-1\text{(Negative)}$

$\text{else }\!\!~\!\!\text{ }{{\text{e}}_{\text{class}}}=1\text{(Positive)}$

Notation Explanation:

$e$ = Voltage error = ${{V}_{ref}}-{{v}_{out}}$ (V)

${{e}_{thr}}=0.03$ = Error threshold (3% of reference)

${{e}_{class}}$ = Error classification (-1, 0, +1)

Error Derivative Classifications:

$\text{if }\!\!~\!\!\text{ }\left| \text{de} \right|<\text{d}{{\text{e}}_{\text{thr }\!\!~\!\!\text{  }\!\!~\!\!\text{ }}}\text{then }\!\!~\!\!\text{ d}{{\text{e}}_{\text{class}}}=0\text{(Zero)}$

$de$ = Error derivative = $\frac{de}{dt}$ (V/s).

$d{{e}_{thr}}=150$ = Derivative threshold.

$d{{e}_{class}}$ = Derivative classification (-1, 0, +1).

Fuzzy Rule Base:

The fuzzy controller uses 9 rules to map error and error rate signals to control actions. The rule structure is as follows:

The complete fuzzy inference rule base is provided in Table 4.

Table 4. Fuzzy inference rule base mapping the error and error rate to the control action

Membership Functions:

Error threshold: ${{e}_{thr}}$ = 0.03 (3% of reference voltage)

Derivative threshold: $d{{e}_{thr}}$ = 150 (calibrated from experimental data).

Output range: duty correction ∈ [-0.15, +0.12].

Fuzzification Process:

if |$e$| < ${{e}_{thr}}$ then ${{e}_{class}}$ = 0 (Zero)

else if $e$ < $-{{e}_{thr}}$ then ${{e}_{class}}$ = -1 (Negative)

else ${{e}_{class}}$ = 1 (Positive)

if |$de$| < then declass = 0 (Zero)

else if de < $-d{{e}_{thr}}$ then $d{{e}_{class}}$ = -1 (Negative)

else $d{{e}_{class}}$ = 1 (Positive)

Defuzzification: The output duty-cycle correction is obtained via direct lookup in a precomputed table indexed by the classified error and error-rate inputs. This approach considerably speeds up computation, making it suitable for real-time control implementations where quick decision-making is crucial.

Performance Benefits:

•Overshoot suppression during large load steps

•Enhanced stability during mode transitions

•Robustness to parameter variations

Improved disturbance rejection

Figure 6 shows the three-dimensional fuzzy-rule surface relating the error inputs to the output correction. Figure 7 shows the transient response with and without fuzzy logic correction enabled.

Figure 6. Three-dimensional fuzzy-rule surface relating error inputs to output correction, with experimentally validated points

Figure 7. Output response with fuzzy logic correction enabled versus disabled

When transient events occur, the fuzzy logic controller improves system performance, reduces overshoot, accelerates settling time, and enhances stability.

5.3 Proportional–integral–derivative-control with mode adaptation

By modifying parameters according to the operating mode, the PID layer enhances steady-state accuracy and gives the MPC output precise control adjustments. This mode-dependent tuning maximizes performance under various circumstances and guarantees stability [7].

Mode-Specific Tuning:

The optimised proportional–integral–derivative parameters and the resulting settling times for each operating mode are listed in Table 5.

Each mode of operation makes use of optimized PID parameters:

Buck Mode:

•K_p = 0.45 (moderate proportional gain).

•K_i = 60 (higher integral gain for steady-state accuracy).

•K_d = 0.005 (low derivative gain to minimise noise).

Boost Mode:

•K_p = 0.35, to enhance system stability by reducing proportional gain.

•K_i = 40, correct steady-state error adequately by offering moderated integral.

•K_d = 0.005, which damps the oscillations with no noise

Buck-Boost Mode:

•K_p = 0.40 (intermediate proportional gain).

•K_i = 50 (balanced integral action).

•K_d = 0.005 (consistent derivative action).

Anti-Windup Implementation:

Integral windup is prevented through clamping:

if ∫edt > 0.2⇒ ∫edt = sign (∫edt) 0.2                (16)

Notation Explanation:

•$\int edt$ = Integral of error (accumulated error over time).

•$\text{sign}\left( \cdot  \right)$ = Sign function (-1 for negative, +1 for positive).

The value 0.2 represents the maximum limit set on the integral term of the PID controller to prevent integrator windup. Figure 8 illustrates the adaptation of the PID parameters and the anti-windup behaviour across mode transitions.

Figure 8. Adaptation of proportional–integral–derivative (PID) parameters and anti-windup behavior across mode transitions

5.4 Type-III compensator design

A digital Type-III compensator provides additional phase boost and shapes the loop dynamics for improved stability margins [9, 10].

Digital Transfer Function:

${{G}_{c}}\left( z \right)={{K}_{c}}\cdot \frac{\left( z-{{z}_{1}} \right)\left( z-{{z}_{2}} \right)}{z\left( z-{{p}_{1}} \right)\left( z-{{p}_{2}} \right)}$                (17)

Notation Explanation:

${{G}_{c}}\left( z \right)$ = Compensator transfer function in z-domain.

${{K}_{c}}$ = Compensator gain.

${{z}_{1}},{{z}_{2}}$ = Zero locations (provide phase boost).

${{p}_{1}},{{p}_{2}}$ = Pole locations (provide high-frequency rolloff).

$z$ = Complex variable in z-domain.

Digital Implementation:

$\alpha ={{e}^{-\omega {{T}_{s}}}}$

Notation Explanation:

$\alpha $ = Digital filter coefficient.

$\omega $ = Analog frequency (rad/s).

${{T}_{s}}$ = Sampling period (s).

Pole-Zero Placement:

Zeros: ${{f}_{1}}$ = 500 Hz, ${{f}_{2}}$ = 2 kHz (phase boost region).

Poles: ${{f}_{1}}$ = 100 kHz, ${{f}_{2}}$ = 150 kHz (high-frequency rolloff).

Digital implementation: $\alpha ={{e}^{-\omega {{T}_{s}}}}$ for each pole/zero.

Phase Margin Optimization:

Despite variations in system parameters the compensator is designed in such a way to achieve approximately 90° phase margin at the crossover frequency to ensures robust stability. Thus, stable operation of the converter across all modes is maintained to prevent oscillations and preserve control performance.

5.5 Control integration and output generation

To optimize the performance of the hybrid control architecture, a systematic sensitivity analysis was conducted using MATLAB/Simulink. In this analysis, the gain factors for mode-adaptive PID (α), fuzzy logic (β), and Type-III compensator (γ) layers were varied individually and in combination, while keeping the MPC core fixed. From simulation results, dynamic and steady-state performance metrics—settling time, output ripple, steady-state error, and overshoot—were extracted for each combination. This approach made it possible to quantify the individual and combined effects of each layer, guaranteeing a stable and well-balanced hybrid control system. A high PID gain (α = 0.5) causes overshoot (2.1% vs. 1.3%) and ripple (0.22% vs. 0.17%), but it also slightly improves settling time (3.0 ms vs. 3.2 ms). Low PID gain (α = 0.1) slows settling time (4.1 ms) while reducing ripple (0.14%). Reduced FLC gain (β = 0.8) increases settling time (3.7 ms) while further suppressing ripple (0.13%). The optimal combination (α, β, γ) = (0.3, 1.0, 0.2) balances all metrics: settling time 3.2ms, ripple 0.17%, steady-state error 0.40%, and overshoot 1.3%. Figure 9 shows the Bode plot comparison of the loop gain.

Figure 9. Bode plot comparison showing loop gain

The final duty cycle is obtained by combining the outputs of the MPC, FLC, PID, and compensator layers using weighted summation, followed by saturation within the limits 0.15 ≤ D ≤ 0.85. A first-order low-pass filter is applied to smooth duty variations and reduce switching noise.

Final Processing of Output Filtering:

${{d}_{filtered~}}\left[ k \right]=0.85\cdot {{d}_{filtered}}\left[ k-1 \right]+0.15\cdot {{d}_{final~}}\left[ k \right]$                    (18)

Notation Explanation:

${{d}_{filtered~}}\left[ k \right]$: Present filtered output.

${{d}_{filtered}}\left[ k-1 \right]$: Previous filtered output.

0.85: Filter coefficient (i.e., 85% of previous value retained).

0.15: Input weight (15% new input contribution per control update).

Architectural Justification:

The gain factors (α = 0.3 for PID, β = 1.0 for FLC, γ = 0.2 for Compensator) are systematically tuned via sensitivity analysis (Table 6) to prioritize the predictive action of MPC and the robust correction of FLC during transients. The PID and Compensator provide finer steady-state regulation and stability. The low-pass filter smooths duty cycle changes across switching cycles and attenuates quantization noise from discrete MPC evaluation.

Table 6. Mode-dependent gain factors (α, β, γ) and the corresponding performance metrics obtained from the sensitivity analysis

Additional Features:

TDM α-adaptation: Power sharing ratio adapts based on measured input power distribution.

Thermal derating: Duty cycle reduction when ${{T}_{j}}$ > 70 ℃ to prevent overheating.

Mode hysteresis: Prevents chattering during voltage boundary crossings.

Figure 10 illustrates the hierarchical signal flow of the proposed hybrid control system. The TDM scheduler selects the active input source and forwards the sampled voltage and inductor current to the controller. The supervisory MPC block computes the predictive duty component; the mode-adaptive PID provides steady-state correction; and the FLC adjusts the control gain to improve transient response under nonlinear conditions. The combined signal passes through the Type-III compensator and PWM generator, producing the gate drive for the EPC2001 GaN devices. This structured flow ensures coordinated operation across all control layers.

Figure 10. Hybrid control architecture and signal flow

5.6 Stability considerations

A rigorous Lyapunov construction for the full hybrid architecture is beyond the scope of this work. Closed-loop stability is instead supported through frequency-domain margins, bounded closed-loop operation, and empirical validation. The three-layer control architecture exhibits timescale separation: the supervisory MPC operates at a slower rate relative to the switching loop, the FLC performs static gain arbitration, and the mode-adaptive PID with Type-III compensator regulates the inner loop dynamics. Closed-loop stability is therefore dominated by the inner regulation loop, whose crossover frequency is placed at approximately 8 kHz with a phase margin of about 90° across all operating modes. The duty cycle is constrained within 0.15 ≤ D ≤ 0.85. Together with bounded FLC outputs and finite MPC candidate selection, this ensures bounded closed-loop behaviour.

These analytical arguments are supported by the 100-run Monte Carlo study and the 72-hour continuous-operation test, where output ripple, efficiency, settling time, and steady-state error remained consistently close to nominal values (0.17% / 0.19%, 91.48% / 91.10%, 3.2 / 3.8ms, 0.40% / 0.41%), confirming stable operation within the tested conditions.

7.1 Prototype implementation

A prototype hardware validates simulation results and exhibits the feasibility of the hybrid control approach.

Hardware Specifications:

PCB: 2-layer FR-4, optimized layout for high-frequency switching.

Switches: EPC2001 GaN FETs (S₁, S₂, S₃) with R_on = 0.3 mΩ @ 25 ℃.

Diodes: CREE C3D02060A SiC Schottky (D₁, D₂) with ${{V}_{f}}$ = 0.3 V.

Inductor: Custom wound ferrite core, L = 180 µH, DCR = 15 mΩ.

Capacitor: Low-ESR polymer, C = 22 mF, ESR < 5 mΩ.

Control: Real-time implementation on TI TMS320F28377S DSP.

7.2 Experimental measurement setup

Details of instrumentation used to observe the key performance parameters. All measurements are conducted under controlled laboratory conditions at approximately 25 ℃ ambient temperature. Figure 20 shows the experimental hardware setup.

Figure 20. Experimental hardware setup

7.2.1 Measurement considerations

Experimental measurements are subject to sensor accuracy, switching noise, and environmental variations. Voltage and current measurements carry uncertainties within ±1–2%, and efficiency within ±0.5%. The measuring instruments used for experimental validation, together with their specifications, are summarized in Table 9. These factors account for the minor deviations between simulation and experimental results reported in Table 10. Figure 21 presents the oscilloscope output waveforms during the switch and diode conduction periods.

Table 9. Measuring equipment

Table 10. Comparison of simulated and experimental performance metrics with absolute and relative deviations

Figure 21. Oscilloscope output waveforms during switch and diode conduction periods

7.3 Experimental results

The experimental results show close agreement with simulation. The output voltage ripple is 0.19% compared to 0.17% in simulation, while efficiency is 91.1% versus 91.48%. The settling time shows a higher deviation (3.8 ms compared to 3.2 ms), attributed to switching non-idealities and practical implementation effects.

Thermal Validation:

Switch Temperature: 37–39 ℃ (measured) Vs. 36.7 ℃(simulated)

Diode Temperature: 32–34 ℃ (measured) Vs. 31.7 ℃ (simulated)

Ambient Temperature: 25 ℃ ± 1 ℃ during all measurements. Figure 22 compares the theoretical and experimental output voltage, inductor current, and duty cycle. Figure 23 compares the experimental and simulated Bode plots.

Figure 22. Comparison of theoretical and experimental output voltage, inductor current, and duty cycle

Figure 23. Experimental versus simulated Bode plot

Frequency Response Validation:

Closed-loop system test confirms designed stability margins:

Measured Phase Margin: 85–90° (across all modes).

Simulated Phase Margin: 90° (design target).

Crossover Frequency: 7.8–8.2 kHz (measured) Vs. 8.0 kHz (designed).

7.3.1 Consolidated simulation and experimental comparison

To provide a clear and traceable comparison of performance metrics, Table 10 summarizes key simulation and experimental results. Table 10 deviations are consistent with experimental variations commonly observed in hardware validation of power electronic converters and are attributed to parasitic effects, switching non-idealities, and measurement uncertainty.

7.4 Long-term reliability testing

Extended operation testing validates thermal stability and component stress levels:

Test Conditions:

Duration: 72 hours continuous operation.

Load Profile: Periodic 3.5 Ω ↔ 1.8 Ω steps every 30 seconds.

Temperature Cycling: 25 ℃ to 60 ℃ ambient variation.

Voltage Variations: ±5% input voltage.

Results:

All key electrical performance metrics remain within expected experimental variation ranges over the test duration.

Thermal Stability: Junction temperatures remain below 45 ℃ maximum.

Component Stress: No visible degradation or parameter drift observed.

To evaluate long-term operational stability, a 72-hour continuous test was conducted under dynamic load conditions.

Table 11. 72-hour reliability results

The results in Table 11 demonstrate stable operation, with output ripple, efficiency, and device temperatures remaining consistent over time, confirming the thermal and electrical reliability of the proposed system. The suggested work outperforms single-loop MPC [11] and FLC-only [12] techniques, demonstrating benefits across all measures. Superior efficiency and thermal performance are achieved by combining GaN/SiC devices with a thorough thermal model. The key advancements of the proposed work relative to existing approaches are summarized in Table 12.