Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

An extensive body of literature exists on the topic of LDPC decoding approaches and their implementation, underscoring their significance in the realm of communication systems. The implementation of these codes on Field Programmable Gate Array (FPGA) devices exhibits considerable variation, stemming from factors such as algorithm type, LDPC type, and specific implementation objectives. These objectives can range from enhancing performance and reducing complexity to increasing throughput.

Upon reviewing the existing literature, several prominent types of LDPC decoder algorithms emerge:

(1) The Min-Sum decoding algorithm and its associated significance.

(2) The architecture of parallel layout decoding.

(3) The semi-parallel LDPC decoding architecture.

These types and their related studies are explored in the ensuing discussion.

In recent years, a comprehensive survey was conducted by Shao et al. [20], wherein a detailed analysis of Turbo, LDPC (Low-Density Parity Check), and Polar decoder Application-Specific Integrated Circuit (ASIC) implementations was performed. The examination of these coding schemes focused on their use in cellular communication systems, with a particular emphasis on the transition from Turbo to LDPC and Polar codes in 5G New Radio (NR) data and control channels.

A myriad of factors was considered in the evaluation, drawing from ASIC implementations across assorted sources. These factors included computational complexity, volume, error correction capability, flexibility, area efficiency, and energy efficiency. Moreover, it was established that LDPC codes outperformed Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) algorithms for extended codeword lengths, exhibiting a robustness and parallelism superior to Hamming, Reed-Solomon, and Reed-Muller codes in high-bit error rate scenarios [21].

In comparison to turbo codes [22], LDPC codes demonstrated superior performance with considerable block lengths, offering flexibility, ease of theoretical verification, and practical implementation. They exhibited reduced complexity, efficient computation, support for parallel processing, and high throughput for swift decoding processes. These characteristics underscore the potential and applicability of LDPC codes in contemporary communication systems.

The prominence of LDPC decoding algorithms, most notably the soft decision and min-sum algorithms, is largely attributable to their demonstrable effectiveness and precision in error correction. In an investigation undertaken by Hussein et al., an evaluation of soft decision decoding algorithms' performance for LDPC codes on Additive White Gaussian Noise (AWGN) channels was conducted, with the Bit Error Rate (BER) as the primary focus. The Min-Sum algorithm was found to surpass other algorithms in a range of circumstances, delivering superior results [23].

In a comprehensive literature review by Roberts and Anguraj, LDPC decoding algorithms and their applications were meticulously examined and classified based on various criteria, including performance, similarities, scalability, numerical stability, and hardware feasibility. A comparative study by Zhou et al. pitted several methods against each other—BF, WBF, BP, and LLR—to ascertain the top-performing algorithm through a performance analysis of LDPC decoding algorithms. Their findings suggested that the NMS algorithm outperformed the others, showcasing lower complexity and superior performance [24-26].

These studies collectively offer invaluable insights into the performance of LDPC decoding algorithms and their practical applications.

A number of research efforts have been directed towards enhancing the hardware efficiency, throughput, and error correction of LDPC decoding algorithms. In one such study, an Offset Min-Sum (OMS) algorithm for a hardware-efficient Quasi-Cyclic LDPC (QC-LDPC) decoder was proposed, which achieved high throughput. However, this study also underscored the significant developmental costs associated with high-throughput LDPC decoders [27].

In another investigation, the throughput and hardware usage efficiency for regular and irregular LDPC codes were augmented using the Minimum-Sum (MS) algorithm on the base matrix (BG1) of the 5G standards. It was noted that while more iterations improved error correction, they concomitantly increased the decoding time [28].

In a different study, LDPC codes and the Min-Sum algorithm were implemented in a Differential Chaos Shift Keying (DCSK) communication system, resulting in improved BER performance and real-time processing efficiency on a Xilinx Kintex7 FPGA platform [29].

These studies collectively contribute to the advancement of LDPC decoding algorithms, augmenting hardware efficiency and BER performance. However, they simultaneously draw attention to the challenges posed by development costs and increased decoding time for high-throughput LDPC decoders and iterative processes.

Several studies have been embarked upon to refine LDPC decoding techniques applicable to a variety of communication systems. In one such investigation [30], the smOMS algorithm was employed to optimize Min-Sum decoding for irregular 5G NR LDPC codes. This technique was found to reduce hardware requirements and effectively manage the Signal-to-Noise Ratio (SNR) dips caused by the irregularity of 5G NR codes. The same study also highlighted the potential of partial parallel LDPC to improve 5G NR Bit Error Rate (BER).

In the study of Liu et al. [31], the Threshold-Attenuated Min-Sum Algorithm (TAMSA) was adapted for a (155, 64) QC-Tanner code LDPC decoder. This approach was observed to augment the BER without necessitating additional hardware. The layered TAMSA was introduced as a cost-effective solution with superior hardware capabilities. The suitability of LDPC for 5G NR was scrutinized in this study, with a particular emphasis on error correction.

Further, the potential of a high-speed, low-complexity LDPC decoder employing the SAMS algorithm was explored [32]. This decoder was capable of achieving a throughput of 10.5 Gb/s while sustaining an acceptable Bit Error Rate (BER). It addressed the challenges of routing congestion and power utilization and was designed specifically for millimeter-wave 60-GHz systems, outperforming previous designs.

Additional contributions to the understanding and development of LDPC coding techniques were made in two pivotal studies [33, 34]. One of these studies conducted an evaluation of LDPC code designs on FPGA devices, focusing on adaptability, processing speed, and parallelism. The study classified critical factors in FPGA-based LDPC decoder design, underlining the distinctions between LDPC code designs and their performance characteristics. Another comprehensive review of recent advancements in LDPC decoding algorithms was undertaken, discussing their role in error control coding and highlighting both algorithm-driven and hardware-realization-based approaches.

Several studies have ventured into the domain of FPGA-based LDPC decoder designs for diverse LDPC codes and communication standards. In the study of Likhobabin et al. [35], a highly parallel decoder that leverages Min-Sum decoding was proposed. This decoder demonstrated a throughput of up to 500 Mbps for QC-LDPC codes under the DVB-S2X standard. Nevertheless, it was challenged by long code words and large matrices.

A subsequent work centered on 5G QC-LDPC codes and introduced a highly parallel and adaptable decoder architecture that achieved a processing rate of 10 GB/s [36]. However, the flexibility of the architecture imposed certain limitations on hardware design. An additional study utilized FPGA-based parallel layered decoding with adaptive normalization for 5G NR LDPC codes [37]. While it offered remarkable scalability for varying lifting factors and enhanced decoder BER performance, it was observed to potentially experience reduced throughput with minor lifting factor values. These designs collectively aimed to strike a balance between high throughput and hardware constraints, catering to a variety of code configurations and matrix sizes.

Further strategies to enhance LDPC encoding and decoding techniques were proposed in subsequent studies [38-40]. One such investigation proposed a high-throughput IR-QC-LDPC encoding and decoding method that utilized a normalized min-sum algorithm (NMSA), achieving a decoding throughput of 27.85 Mbps when implemented on an FPGA. The conversion of quasi-cyclic LDPC codes into block quasi-cyclic LDPC codes was also explored, resulting in an impressive throughput of 2.97 Gbps after five iterations on the FPGA. Another study demonstrated an FPGA implementation of a low-complexity regular LDPC decoder capable of achieving a high data rate with low latency.

In the realm of LDPC codes, numerous significant contributions have been made, leading to a broad spectrum of applications across varied domains. Exploration of their potential for the forthcoming generation of IoT networks has been undertaken. For instance, a Dual Min-Sum (DMS) architecture for LDPC codes in the context of IEEE 802.16e was introduced [41], which exhibited superior error correction performance.

Attention was also directed towards LDPC decoders for Wi-Fi in another study of Tsatsaragkos and Paliouras [42], where effective decoding algorithms and interconnection techniques were established for achieving high throughput. Additionally, a serial LDPC decoder that accomplished substantial speedups on a System-on-Chip platform was presented [43, 44]. This was particularly evident at low signal-to-noise ratios. The same study also demonstrated the use of a DE1-SoC FPGA-based information transceiver board for LDPC coding, achieving minimal errors and an impeccable 0% error rate during data transmission through UART serial communication.

Moreover, a semi-parallel LDPC decoding architecture was proposed [45], which amplified throughput for solid-state drives, albeit at the expense of increased hardware overhead. These studies collectively offer valuable insights into the design and optimization of LDPC decoding for various applications and code types.

The tables provided contain comprehensive information on a plethora of studies pertaining to LDPC codes. Table 1 primarily focuses on recent research conducted in the field, including the authors, year, and research concept. Conversely, Table 2 ventures into an in-depth exploration of different types and methods of LDPC codes, their implementation approaches, and the challenges encountered in recent times. Specific LDPC code constructions, employed decoding algorithms, and performance analysis under various channel conditions may also be included in the table. Furthermore, it encompasses the advantages and drawbacks of the LDPC codes.

Overall, these studies and tables provide a rich tapestry of research in the field of LDPC codes, enhancing our understanding of their potential and the challenges associated with their implementation in various contexts.

Table 1. Studies reviewed in the last few years

Table 2. The LDPC type and method, implementation method and challenges in the last few years

LDPC decoders play a pivotal role in modern communication systems. They are essential for ensuring data's reliable and error-free transmission in a wide range of applications. In this discussion, we will explore LDPC decoder implementation, decoding algorithms, and architectural aspects:

4.1 LDPC decoder implementation

The LDPC decoder architecture is a critical component of communication systems, but its effectiveness hinges on proper implementation. This entails meticulous design and configuration to ensure it functions optimally for error correction. The choice of hardware, such as field-programmable gate arrays (FPGAs), plays a pivotal role in achieving efficient LDPC decoding. Field-programmable gate arrays are a crucial technology used in LDPC decoder implementation. They offer the advantage of reconfigurability, enabling them to be tailored to the specific requirements of LDPC decoding. They are highly efficient for parallel processing and essential for handling large amounts of data in real-time, a common requirement in communication systems.

Additionally, LDPC decoding's throughput and complexity are influenced by factors such as codeword length in bits, code rate (the ratio of information bits to codeword length), computation complexity at each processing node, interconnection complexity, and the number of local computation iterations. Achieving a balance between decoder performance, complexity, and speed is crucial [57, 58].

4.2 Decoding algorithms

LDPC decoding algorithms typically function by employing either hard decisions (e.g., bit flipping, BF) or soft decisions (e.g., sum-product, SP, and min-sum, MS) using incoming messages from the noisy channel, as illustrated in Figure 3 [59]. Better bit error rate (BER) performance can be achieved with soft decision decoding algorithms, which take as input the channel probabilities expressed as a logarithmic ratio, also referred to as a log-likelihood ratio (LLR), however, hard decision-decoding algorithms, are simple and fast, and their hardware implementations are easy [60]. The following is an elucidation of some algorithms utilized in LDPC decoding:

The bit-flip (BF) algorithm is a hard, decision-oriented decoding approach. Once the encoded message from the channel is received, a binary decision is made and sent to the decoder. When it comes to implementing algorithms in hardware, the bit-flip algorithm is the most straightforward because of the simplicity of its check nodes and variables. However, the algorithm has low BER performance because it employs a hard-decision approach, making binary choices based on received channel data and oversimplifying the information by not considering the probabilities associated with different bit values. This binary decision-making can lead to incorrect bit flips in noisy channel conditions, resulting in higher decoding errors. In contrast, soft-decision algorithms use log-likelihood ratios (LLRS) for a more nuanced representation of bit likelihood, making them more accurate in noisy conditions due to their ability to make probabilistic judgements about transmitted bits [61].

4.2.1 Variable node operation for BF

$V_n \begin{cases}0 & \text { If majority }\left(C_i\right)=0 \\ 1 & \text { If majority }\left(C_i\right)=1 \\ V_n & \text { Otherwise }\end{cases}$      (1)    

where, n= 1, 2, …, N (variable nodes).

i= 1, 2, ..., dv (degree of variable node "n")

4.2.2 Check node operation for BF

${{C}_{k}}={{V}_{1\ \ }}\oplus \ {{V}_{2}}\oplus ..\oplus \ {{V}_{l\ \ \ \ }}\forall l\ne k$                 (2)

where, l, k= 1, 2, ..., dc (degree of check node)

The Sum of Products Algorithm (SPA) is a soft decision message-passing algorithm that involves LLR (intrinsic message) variable node operations to facilitate decoding decisions. Eq. (3) illustrates the transmission of LLRs to variable nodes for decoding. The input LLRs are summed at the v-nodes, and the resulting computed (extrinsic) messages are communicated to the c-nodes via the connected edges (C). The function of the check nodes (C) is denoted by equation (4). The corresponding variable nodes receive the output messages. Check nodes also do parity checks. This process is repeated until the maximum number of iterations has been reached or the parity test has been passed.

The Sum of Products Algorithm (SPA) offers excellent decoding performance is primarily attributed to its soft decision-making capabilities, iterative processing, and adaptability, which allow it to handle noisy channels and provide accurate error correction effectively [62]. However, it does come with its share of challenges and drawbacks. These can include computational complexity due to the nonlinear operations performed at the check nodes, which can be resource-intensive and time-consuming. Additionally, transmitting high-precision extraneous messages between nodes requires significant computational effort. These factors contribute to the algorithm's computational load and can impact its real-time processing capabilities, making it less suitable for applications where low latency is crucial. Moreover, while the SPA provides high-quality error correction, it may not be the most power-efficient solution, making it less ideal for energy-constrained devices.

4.2.3 Variable node operation for SPA

${{V}_{i}}=LL{{R}_{n}}+\sum\limits_{j\ne i}{{{C}_{j}}}$             (3)

where, i, j = 1, 2, ..., dv (degree of variable node "n").

4.2.4 Check node operation for SPA

${{C}_{k}}=2{{\tanh }^{-1}}\ \left( \prod\limits_{k\ne l}{\tanh }\frac{{{V}_{l}}}{2} \right)\ $                (4)

where, l, k = 1, 2, ..., dc (degree of check node).

The Min-Sum Algorithm (MSA) is a simplification of the SPA. As shown in Eq. (5), the check node operation is streamlined to simplify the algorithm. The MSA is easy to implement in hardware because it uses simple math and logic operations.

On the other hand, quantizing the soft input messages greatly affects how well the algorithm works [63]. There are many MS algorithm variants, such as "offset min-sum" [64], "normalized min-sum" [65], and "adaptive quantization in min-sum" [66]. To boost the MS algorithm's BER performance, these alterations are proposed.

4.2.5 Check node operation for MSA

${{C}_{k\ \ }}=\prod\limits_{l\ne k}{sign\left( {{V}_{l}} \right)\ }\times \ \underset{l\ne k}{\mathop{\min }}\,\left| {{V}_{l}} \right|$              (5)

where, l, k= 1, 2, ..., dc (degree of check node).

Layered decoders are often used in the LDPC because they can do calculations quickly and are built consistently [67]. Vertically stacked decoding and horizontally layered decoding are two types of layered decoding schemes.

3.png

Figure 3. Types of LDPC decoding algorithms

4.3 LDPC decoder architectures

There are several types of architectures associated with LDPC decoder design, including:

(1) Parallel: This architecture provides exceptionally low power dissipation and great throughput but is inefficient in the area [68].

(2) Serial: The parallel technique results in an incredibly complicated interconnection challenge. A sequential decoding machine is used to avoid this issue, which processes the input nodes in a linear order from the first bit-node to the last in each iteration [69].

(3) Semi-parallel: The semi-parallel decoding design provides a better combination of throughput performance and hardware requirements, making it an excellent choice for QC- LDPC codes. This type of architecture generally delivers a fair trade-off between hardware complexity and decoding throughput [70].

(4) Minimum semi-parallel: This architectural design exemplifies the disparity in performance and complexity between semi-parallel and serial decoders. The architecture demonstrates commendable suitability and proficiency in accommodating high-performance applications, particularly those that impose significant demands on wireless and mobile systems as well as portable devices. One of the primary difficulties associated with Low-Density Parity-Check (LDPC) codes pertains to their pragmatic application [71].

The main challenge of LDPC decoders is their complexity. LDPC decoders require much computing power to decode messages, making them difficult to implement in real-time applications such as wireless communication in cellular networks, autonomous vehicles relying on real-time data processing, and platforms offering live video streaming, where LDPC's computational demands can strain processing resources and cause latency issues.

Additionally, the codes used by LDPC decoders are often very long, making them difficult to store and transmit. Nevertheless, the main advantage of LDPC decoders is their accuracy. LDPC decoders can detect and correct errors with high accuracy, making them ideal for applications where data integrity is essential. For instance, in satellite communication systems. Furthermore, LDPC decoders can effectively detect errors in data corrupted by noise or interference, making them well-suited for use in noisy environments by iteratively exchanging messages between check nodes and variable nodes in a graphical representation, making probabilistic judgments about bit values through log-likelihood ratios (LLRs), and refining these assessments until convergence or parity checks are satisfied, allowing them to offer robust error correction in such conditions. Overall, LDPC decoders are a powerful tool for improving communication reliability, but they come with challenges and advantages. While they require a large amount of computing power and can be difficult to store and transmit, they offer high levels of accuracy and are well-suited for use in noisy environments [80-82].