Modeling of Railway Logics for Reverse Engineering, Verification and Refactoring

Modeling of Railway Logics for Reverse Engineering, Verification and Refactoring

F. Flammini | A. Lazzaro | N. Mazzocca 

ANSALDO STS, RAMS Unit, Via Nuova delle Brecce 260, Naples 80147, Italy

University of Naples “Federico II”, Dipartimento di Informatica e Sistemistica, Via Claudio 21, Naples 80125, Italy

Page: 
77-94
|
DOI: 
https://doi.org/10.2495/SAFE-V1-N1-77-94
Received: 
N/A
| |
Accepted: 
N/A
| | Citation

OPEN ACCESS

Abstract: 

Model-based approaches are widespread both in functional and non-functional verification activities of critical computer-based systems. Reverse engineering can also be used to support checks for correctness of system implementation against its requirements. In this paper, we show how a model-based technique, using the Unified Modeling language (UMl), suits the reverse engineering of complex control logics. UMl is usually exploited to drive the development of software systems, using an object-oriented and bottom-up approach; however, it can be also used to model legacy non-object-oriented logic processes featuring a clear distinction between data structures and related operations. Our case-study consists in the most important component of the European Railway Traffic Management System/European Train control System: the Radio Block center (RBc). The model we obtained from the logic code of the RBc significantly facilitated both structural and behavioral analyses, giving a valuable contribution to the static verification and refactoring of the software under test.

Keywords: 

control software, modeling, railways, refactoring, reverse engineering, verification

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