Accurate Power Estimation Identity for DSP Blocks Targeted to FPGAs

Elleouet et al. [3] have anticipated an identity that could estimate the power of a system designed using N IP cores. Architectural and algorithmic parameters have been used for projecting the model. The analysis is based at the system level. Jevtic et al. [4] have proposed a model that could estimate the power of multiplier blocks in FPGAs. They discovered a void in David Elleouet and Nathalie Choy’s work. According to their detections, interconnect and component powers have not been divided separately which may cause accuracy issues for complex designs. Lorandel et al. [5] have presented a method that could evaluate the power of wireless communication systems at a higher abstraction level. The proposed methodology is specific to a wireless communication system. Also, in their work emphasis has not been put on how the power is influenced after interconnecting various IP blocks. Deng et al. [6] have presented curve-fitting and regression-based models that could accurately estimate the area, time and power. Their work is on IP cores-based implementations for FPGAs. This designing approach will greatly enhance the hardware development efficiency. Gebotys et al. [7] have presented a linear regression-based model that could predict the power. They derived variables from the DSP code for formulating the models and achieved an error of less than 4%. Verma et al. [8] have applied the statistical power estimation technique for estimating the power of embedded systems. The analysis has been carried out for almost 30 circuits and power has been estimated using Xpower Analyzer. They found that the statistical-based power estimation technique provides good accuracy with a faster estimation speed. Nasser et al. [9] in their paper have presented an overview of power modeling and estimation techniques at different abstraction levels (from RTL to the transistor). They found that the simulation-based estimation technique is generic and estimates power accurately with a longer estimation time. However, the probabilistic-based approach provides low accuracy, but higher estimation speed. Referring to various works, they also agreed to the fact that the statistical-based estimation technique provides moderate accuracy with moderate estimation speed. Raghunathan et al. [10] have proposed a statistical modeling technique at the RTL level that could estimate switching activity and power consumption. In their work, they have considered glitches to achieve better accuracy. An error of about 7% has been achieved. Makani et al. [11] worked on resource utilization report from hardware. They carry out analysis for estimating the area and power without RTL implementation. Durrani and Riesgo [12] have proposed a modeling technique at the architectural level that could estimate the power based on the knowledge of input/output. Similar to Elleouet et al. [3] they have also claimed that the fast power estimation of IP-based designs can be achieved by simply adding the power consumed by the individual IP cores. They have achieved the error of 1-2% for individual macro-blocks and 9-15% for the complete system. They have also not focused on how the power would get influenced once the various IP blocks are interconnected to form a complete system. Singh et al. [13] have proposed Artificial Neural Network (ANN) and regression-based model for an embedded multiplier. As per their finding the proposed models are generic for all 7-series FPGAs devices. Therefore, in this work, while designing a complete system using different IP cores, the focus has been laid on interconnection power.

From the literature survey, it has been analyzed that various power modeling and estimation techniques have been established in literature at a different abstraction level. It has been seen that the statistical based modeling technique is providing better accuracy and estimation speed. Various works have been reported in the literature for power estimation at RTL level, but it is limited to individual blocks only. Very few works have been reported related to IP modelling approach for complete system. Therefore, power estimation of systems designed using IP cores is still in the primary phase. Thus, power estimation at RTL level based on IP modeling can prove to be an exceptional profusion due to technology independence and lesser simulation run-time.

In FPGAs, the power consumption has increased due to the large count of programmable switches and interconnects. The total power, Power_(T) in FPGA is sum of static power, Power_(S) and dynamic power, Power_(D) as given by Eq. (1).

${Power}_{(T)}={Power}_{(D)}+{Power}_{(S)}$                     (1)

Static power is not instantaneous for a particular FPGA device and it occurs due to leakage mechanism in MOS transistors, and leakage mechanism itself is a function of the temperature. In this work, no significant rise is observed in temperature while analysis, hence the static power is assumed to be constant i.e., 120mW. However, dynamic power change instantly and is given by Eq. (2).

$\operatorname{Power}_{(D)}=\alpha \times f_{c l k} \times C_L \times V_{D D}{ }^2$                           (2)

where, C_L is the total capacitance, V_DD is the supply voltage, α is the switching activity and f_clk is the clock frequency as per the design requirement [14-18]. Vivado tool estimate the value of α at various nodes of circuit under consideration using a vector-less algorithm. So, control over α is not possible when circuits are designed by interconnecting various IP blocks. Hence, in FPGAs, dynamic power can be given by Eq. (3).

$Power_D=( Signal + Logic +I / O+ Clock+ Memory +D S P) Power$                       (3)

where, I/O power depends on the total number of input/output pins. The average power disbursed by the clock web is the clock power. This also includes power spent by buffer and routing resources. Average power spent by interconnects is termed as the signal power. Logic power is a function of Configurable Logic Blocks (CLBs). This includes power spent by Look-up- Tables (LUTs) and Flip-Flop (FF). Memory power depends upon memory elements. DSP power is a function of number of DSP blocks used in the particular design [5].

Curve-fitting and regression-based model for individual IP cores have been created based on the resource utilization data obtained after synthesis [20-22]. In this work, curve fitting and regression techniques is used to predict the relationship between the dependent and independent variables. Each model has been tested for accuracy against commercial tool. Parameters used and their connotation is explained in Table 3.

Table 3. Parameters used and their connotation

6.1 Regression model for divider

Divider IP is instantiated using different configuration. The dynamic power equations obtained using curve-fitting and regression technique are given by Eq. (4) to Eq. (7). Power obtained for different divider configuration is given in Table 4.

$Outputpower =1.185 \times out\_pin -1.308$                            (4)

$Clockpower =-2.437+0.1583 \times lut -0.0548 \times f f$                           (5)

$Logicpower =1.475-0.0428 \times l u t+0.0232 \times {ff}$                                     (6)

$Signalpower =0.2327+0.003029 \times lut +0.008581 \times f f$                          (7)

Table 4. Comparative analysis of embedded divider block

The power values gained from regression model has been tested for accuracy with reference to the commercial tool using Eq. (8).

${Error}(\%)=\left|\left(\frac{e_i-r_i}{r_i}\right)\right| \times 100$                          (8)

where, e_i is the measured power from regression-based model [14]. r_i is the power value gained from the Vivado tool. Other IP cores have also been validated using same method. From the analysis it has also been seen that the contribution of input power that depends on the number of input pins in the design is less than 1% to the total power. Thus, while modeling it has been assumed to be zero.

6.2 Regression model for 8:1 MUX

Mux IP is instantiated using different configuration. The dynamic power equation obtained using curve-fitting and regression technique are given by Eq. (9) to Eq. (12). The comparative analysis of 8:1 MUX IP for different configuration is given in Table 5.

Table 5. Comparative analysis of MUX block

$Outputpower \left.=79.76 \times \exp ^{\left(-\frac{ { out\_pin }{-}18.23}{11.88} \quad \right)}\right.^2$                          (9)

$Clockpower =1.42 e^{-15} \times( { lut })^{8.831}+0.9989$                            (10)

$Signalpower=20.41 \times \exp ^{\left(-\frac{ { lut-36 }}{6.91} \quad \right)^2}$                            (11)

$Logicpower =20.41 \times \exp \left(-\frac{l u t-36}{6.91}\right)^2$                            (12)

6.3 Regression model for full adder

Full adder IP has been used in many designs. The IP is instantiated using different configuration. The dynamic power equation obtained using curve-fitting and regression technique are given by Eq. (13) to Eq. (16). The comparative analysis for different configuration is given in Table 6.

Table 6. Comparative analysis of full adder block

$Outputpower =0.5294 \times out\_pin +0.1688$                          (13)

$Logicpower =0.0001$                            (14)

$Signalpower =0.0001$                            (15)

$Clockpower =1$                               (16)

6.4 Regression model for multiplier

Multiplier IP is instantiated using different configuration. The dynamic power equation obtained using curve-fitting and regression technique are given by Eq. (17) to Eq. (20). The comparative analysis report for multiplier IP can be referred from [14].

$Outputpower =1.171 \times out\_pin -2.18$                             (17)

$\begin{aligned}  { DSPpower }&=3.372-5.57 \times \cos (D S P 48 \times 0.3927) \\ &+2.671 \times \sin (D S P 48 \times 0.3927) \\ &+2.04 \times \cos (2 \times D S P 48 \times 0.3927) \\ &+0.965 \times \sin (2 \times D S P 48 \times 0.3927) \end{aligned}$                           (18)

$\begin{aligned} { Clockpower }=& 0.6464-0.5 \times \cos (f f \times 0.0462) \\ &+1.207 \times \sin (f f \times 0.0462) \\ &+0.85 \times \cos (2 \times f f \times 0.0462) \\ &-0.146 \times \sin ((2 \times f f \times 0.0462)\end{aligned}$                               (19)

$Signalpower =2.446 \times e^{(0.0103 \times f f)}-1.646 \times e^{(-1.191 \times f f)}$                            (20)

6.5 Regression model for 2:1 MUX

This IP has been customized for different input configuration. Curve-fitting and regression techniques have been applied for creating model based on synthesis report. Dynamic power equations are given by Eq. (21) to Eq. (24). The comparative analysis for different configurations is given in Table 7.

$Outputpower =0.3069 \times out\_pin +0.2721$                              (21)

$Clockpower =8.375 e 14+0.03299 \times f f-8.375 e 14 \times l u t$                            (22)

$Logicpower =0.0001$                            (23)

$Signalpower =1$                            (24)

Table 7. Comparative analysis of 2:1 MUX block

6.6 Regression model for adder/subtractor

Adder/subtractor IP is instantiated using different configurations. The dynamic power equation obtained using curve-fitting and regression technique are given by Eq. (25) to Eq. (28). The comparative analysis result of delay IP for different configuration can be referred from [14].

$Outputpower =0.8744 \times (out\_pin )-0.2083$                                 (25)

$Clockpower =1-0.0147 \times lut +0.0147 \times f f$                               (26)

$Signalpower =1.167+2.039 \mathrm{e} 14 \times {ff}-2.039 \mathrm{e} 14 \times lut$                     (27)

$Logicpower =0.0001$                          (28)

6.7 Regression model for AND gate

IP is instantiated using different configuration. Model has been created based on synthesis report. The dynamic power equation obtained using curve-fitting and regression technique are given by Eq. (29) to Eq. (32). This model is also applicable for OR gate, XOR gate and NOT gate used in the ALU design. Comparative analysis for different configuration is given in Table 8.

$Outputpower =4.769 \times out\_pin -0.2205$                        (29)

$Logicpower =-213.9 \times \exp^{(-2.683 \times lut )}+1.001$                     (30)

$Clockpower =8.007-5.005 \times \cos ( lut \times 0.0938)$$-3.231 \times \sin ($ lut $\times 0.0938)$

$-1.582 \times \cos (2 \times lut \times 0.0938)-0.02673 \times {Sin}(2 \times lut \times 0.0938)$                    (31)

$\begin{aligned} { Signalpower }=& 0.9166-0.177 \times \cos ( { lut } \times 0.1848) \\ &-0.1096 \times \sin ( { lut } \times 0.1848) \\ &-0.3403 \times \cos (2 \times \ { lut } \times 0.1848) \\ &-0.6834 \times \sin (2 \times { lut } \times 0.1848) \end{aligned}$                       (32)

Table 8. Comparative analysis of AND gate block

6.8 Regression model for delay

Delay element is created using D FF. The delay IP has been modified for different input vector length. The dynamic power equation obtained are given by Eq. (33) to Eq. (36). The comparative analysis result of delay IP for different configuration can be referred from [14].

$\begin{aligned} { Outputpower }=&-4.732 e-6 \times( { out\_pin })^4 \\ &+0.0006839 \times( { out\_pin })^3 \\ &-0.03175 \times( { out\_pin })^2 \\ &+0.5956 \times( { out\_pin })-1.965 \end{aligned}$                          (33)

$Clockpower=-1.517-0.2191 \times lut +0.388 \times {ff}$                        (34)

$Logicpower =0.0001$                        (35)

$Signalpower =0.2241-0.1043 \times f f+0.07425 \times lut$                        (36)

6.9 Regression model for accumulator

Table 9. Comparative analysis of embedded accumulator block

The accumulator is customized for different output width. Analytical model has been created using post synthesis report. Equations for dynamic power obtained using curve-fitting and regression techniques are given by Eq. (37) to Eq. (39). Comparative analysis for different accumulator configuration is given in Table 9.

$Outputpower =1.195 \times out\_pin -0.402$                         (37)

$Logicpower =0.0001$                          (38)

$Signalpower = Clockpower =1$                             (39)

Analysis for various DSP blocks has been carried out at 125 MHz frequency. The comparison results for cascaded and non- cascaded DSP blocks with reference to commercial tool have been shown in Figure 3 and Figure 4 respectively. From the results obtained it has been analyzed that the model proposed by Elleouet et al. [3] is working reasonably accurate for non-cascaded blocks. The maximum error obtained for complex non-cascaded blocks such as carry ripple adder is 3.96% as shown in Figure 6. But the percentage error is very large for cascading blocks with more complexity such as FIR filter, ALU, MAC unit, barrel shifter etc. For SISO cascading block, the percentage error obtained using Elleouet et al. [3] identity is 2.52% as its architecture is fairly simple. It consists of only D flip-flop IPs. However, the error is reduced to 0.08% using proposed identity.

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Figure 3. Power analysis of cascaded DSP blocks

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Figure 4. Power analysis of non-cascaded DSP blocks

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Figure 5. Error analysis of cascaded DSP blocks

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Figure 6. Error analysis of non-cascaded DSP blocks

The error obtained for complex cascading circuits with reference to the power values from the commercial tool indicates that the identity proposed by Elleouet et al. [3] is providing inaccurate results particularly for cascaded systems. But, when the power is calculated for cascaded systems using the proposed identity, the error obtained against commercial tool is very low. The maximum error obtained for fairly complex circuit i.e., ALU is only 6.97%. The graph of error for cascading DSP blocks shown in Figure 5 indicates that the proposed identity based on IP modeling is accurately measuring the power for cascaded DSP blocks. Since the proposed identity in this work is same as Elleouet et al. [3] identity for non-cascading DSP blocks, the error values obtained for non-cascading DSP blocks using proposed identity is same as obtained using Elleouet et al. [3] identity.

The curve-fitting and regression-based model proposed in this work for individual IP cores is generalized for all frequencies as depicted in Table 12. The resource utilization would remain the same for all frequencies. Since the model proposed for individual IP cores is based on resource utilization it will work accurately for all frequencies. The dynamic power will vary in direct proportion with the frequency. For instance, if at frequency f1 the dynamic power is p1, then at frequency a*f1 the dynamic power would be a*p1. Thus, if we double the frequency, the power will also get double. From the result obtained for multiplier IP core for 8x8 configuration at different frequencies it can conclude that the power at each frequency can be obtained by just multiplying the dynamic power with the scaling factor (i.e. The factor by which frequency is scaled). It can also be concluded from the % error obtained at different frequencies that the proposed model is producing highly accurate results at higher frequencies. Thus, with the proposed methodology total power can be approximated quickly and accurately at different frequencies.