A Low Noise and Power Efficient 45nm GPDK Technology based Highly Stable Current Balancing Logic (HCBL) and Dynamic Logic Circuits for Mixed Signal Systems

A Low Noise and Power Efficient 45nm GPDK Technology based Highly Stable Current Balancing Logic (HCBL) and Dynamic Logic Circuits for Mixed Signal Systems

S Seenuvasamurthi G Nagarajan

Department of ECE, Research Scholar, Pondicherry University,India, Pondicherry Engineering College, Pondicherry

Department of ECE, Professor, Pondicherry University,India, Pondicherry Engineering College, Pondicherry

Corresponding Author Email: 
seenu_er@yahoo.co.in; nagarajanpec@pec.edu
12 December 2016
15 February 2017
31 March 2017
| Citation



Noise is an important factor in the analog and digital circuits which determine the characteristics of the system. There are many sources of noises. Power supply noise caused by circuit switching, crosstalk noise due to capacitive coupling between neighboring interconnects, fluctuations in device parameters due to process variations, noise due to charge sharing and charge leakage in high speed dynamic logic circuits. The work aims at developing a noise robust circuit with high frequency response. The same circuit can be implemented in a dynamic logic system with reduced number of transistor. Also the dynamic logic will have the probability of signal switching activity to be low which will subsequently reduce the power of the system. The circuits have been constructed using cadence ADE and the same has been simulated with Spectra using 45nm GPDK technology. The simulation results show that the power consumption has been reduced multi-fold and the bandwidth has been increased by 102 Hz and the delay is reduced by 50%


Current Balanced Logic, pseudo-NMOS, Noise immunity,  Dynamic logic

1. Introduction
2. Previous works
3. Proposed work
4. Simulation Results

1. D. J. Allstot, S. Kiaei and R. H. Zele, “Analog logic techniques steer around the noise,” IEEE Circuits Devices Mag., vol. 9, pp. 18–21, Sept.1993.

2. H.T. Ng and D. J. Allstot, “CMOS current steering logic for low voltage mixed-signal integrated circuits,” IEEE Trans. VLSI Syst., vol.5, pp. 301–308, Sept. 1997.

3. H. Sakamoto and L. Forbes, “Grounded load complementary FET circuits: Sceptre analysis,” IEEE J. Solid-State Circuits, vol. 8, pp.282–284, Aug. 1973.

4. A. Sedra and K. Smith, Microelectronic Circuits, 4th ed. Oxford, U.K:Oxford Univ. Press, 1998.

5. The International Technology Roadmap for Semiconductors: 1999 Edition, URL: http://www. itr~.net/l999SIARoadmap/Home. htm.

6. A. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr 1995.

7. L. Wang and N. R. Shanbhag, “Noise-tolerant dynamic circuit design,” Proc. of IEEE  Intl. Symposium on Circuits and Systems,  pp. 549-552, May/June 1999.

8. G. Balamurugan and  N. R. Shanbhag, “Energy-efficient dynamic circuit design in the presence of crosstalk noise,” Proceedings of International Symposium on Low-Power Electronics and Design, San Diego, 1999.

9. N. R. Shanbhag, “A mathematical basis for power-reduction in digital VLSI systems,” IEEE Trans. Circuits Systems, vol. 44, No.11, Nov 1997.

10. R. H. Krambeck, C. M. Lee and H.-F.S. Law, “High-speed ‘compact circuits with CMOS,” IEEE J. Solid-state Circuits, vol. 17, pp. 614-619, June 1982.

11. J. J. Covino, “Dynamic CMOS circuits with noise immunity,” ’U.S. Patent 5650733, 1997.

12. G. P. D’Souza, “Dynamic logic circuit with reduced charge leakage,” U.S. Patent 5483181, 1996.44, pp. 935-951, Nov 1997.

13. C. E. Shannon, “A mathematical theory of communication,” Bell System Technical Journal, vol. 27, part I, pp. 379-423, July 1948.

14. R. Gonzales, B. M. Gordon and M. A. Horowitz, “Supply and threshold voltage scaling for low power CMOS,” IEEE Journal on Solid-State Circuits, vol. 32, pp. 1201-1216, Aug. 1997

15. K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson and A. Zaslavsky,“Techniques for designing noise-tolerant multi-level  combinational circuits,” in Proc. Des. Autom. Test Eur., pp. 576– 581, Mar. 2007.

16. I Chyn Wey, You-Gang Chen and An-Yen Wn, “Design and analysis of Isolated  Noise-Tolerant (INT)  Technique in Dynamic CMOS Circuits”, IEEE  Transactions on Very Large Scale Integration (VLSI) Systems, vol 16, No. 12,  pp.  1708-1712, Dec 2008.

17. Frustaci F, Corsonello P, Perri S and Cocorullo G, “High-performance Noise-tolerant  circuit techniques  for CMOS dynamic logic”, IET Transaction of Circuits,  Devices and Systems, vol 2, No.6, pp. 573- 548, Dec 2008.

18. Tezaswi Raja, Vishwani D. Agrawal and Michael L. Bushnell, “Variable Input Delay  CMOS  Logic for Low Power Design” IEEE Transactions on Very Large Scale  Integration (VLSI)  Systems, vol. 17, No.10, pp. 1534-1545, Oct 2009.

19. Ajay Taparia, Bhaskar Banerjee and T. R. Viswanathan, “CS-CMOS: A Low-Noise  Logic Family for  Mixed Signal SoCs”, IEEE Transactions on Very Large Scale  Integration (VLSI) Systems, vol.19,  Issue 12, pp. 2141-2148, Nov 2012.

20. Sandeep Sangwan, Jyoti Kedia and Deepak Kedia, “A Comparative Analysis of  different CMOS Logic  Design  Techniques for Low Power and High  Speed”, International Journal of  Advanced Research in  Electrical, Electronics  and Instrumentation Engineering, vol. 2, No.10, Oct 2013.

21. Araga Y, Nagata M, Van der Plas G and Marchal P, “Measurements and Analysis of  Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits”, IEEE Transaction  on Components, Packing and Manufacturing Technology, vol. 4, No. 6, pp. 1026- 1037, Apr 2014.

22. Bo Zhao and Huazhong Yang, “Supply-Noise Interactions Among Submodules Inside  a Charge-Pump PLL”, IEEE Transactions  on Very Large Scale Integration  (VLSI) Systems, vol. 23, No.4, pp.771-775,  Apr 2015.