An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Many handheld and portable signal-processing devices are parts of our daily life. The Digital signal processor and image processor have required accurate and efficient arithmetic operations for performing fast and efficient real-time applications [1-9]. As its well-known thing, that multiplier is the most utilized component in arithmetic operations. Many researchers' efforts have been directed to develop an accurate and efficient multiplier design [6-13]. Nowadays filters applications required an efficient multiplier design. Especially, FIR, FFT and DCT techniques want an efficient multiplier design for performing well.

Traditional or reported multiplication was limiting performance in terms of accuracy as well as hardware overhead. Logarithm multiplier must have the potential to become an option of a traditional multiplier for real-time digital signal processor [14-19].

Logarithm multiplication operation can be performing in three steps: (1) Conversion of any format numbers into logarithmic numbers, (2) then performed addition on logarithmic numbers, and then (3) convert back into initial format numbers [8]. The pictorial representation of logarithm multiplication is shown in Figure 1. Many methods regarding binary to logarithmic conversion and vice versa have been discussed in the last few years [18-35]. Error creates at the time of logarithmic and antilogarithmic conversion [10]. It shows the utility of an efficient and accurate logarithmic and antilogarithmic conversion process. The frame of remaining paper is as like: Systematic growth of literature is discussed in Section 2. Proposed methodology and possible hardware construction are discussed in Section 3. Results and comparative analysis of reported and proposed design are exploring in Section 4. At last, the pros corns of design are concluded in Section 5.

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Figure 1. Pictorial representation of logarithm multiplication

On behalf of reported design, it was found that error is not uniform in some conditions. For error improving in any straight line, there is a simple approach that can add the difference of approximated value minus actual value. But in many cases, the error varies in a different segment in different percentage [30]. It can’t give a significant result. For the best result, it can sub-divide the entire line into sub-regions and add the mean difference of correction terms in a specified defined range. But, increasing the number of sub-sections has reverse relation with hardware. This research work focuses on error minimization as well as significant hardware gain. The proposed 11-region or 17-region has a proper selection of fractional region which decides the error in that particular region.  It will offer high performance with a small approximation error, shorter delay, and smaller hardware cost compared to the methods [30-35].

It is desirable to have lower error possibility with a sum of multiple regions error correction terms in a defined range. Since we have to compare the performance of proposed methods with reported methods; therefore, we take the same design parameters. In this section, we present the proposed antilogarithmic converters for 11-region and 17-region error correction. Multi-region error correction adder and subtractor circuit can be used to achieve better design trade-off among accuracy, area consumptions and speed by using the proper selection of fractional region decides the error in that particular region. Deciding the fractional region is a key factor that generates an error multiple of power 2 or as-near-possible to that. Error decides the subtraction term. Since optimized hardware gives an extra advantage to reported methods. Therefore, we minimize hardware. We have a straight-line ax+b. The entire straight line of the error correction scheme is segmented into 11-region and 17-region. It lies between 0 and 1, and to add or subtract the corresponding error correction scheme values. Here, it is worth mentioning that a small error percentage at the first and last region was found so, there is no need to apply the error correction scheme at these first and the last region.

3.1 Proposed method

The proposed piecewise-linear approximation is given by Eq. (1) and error percent is given in Eq. (2).

\(\text{Y}={{2}^{k'}}{{2}^{m'}}\)     (1)

where, k' is any integer and m' lies between zero and one.

\(\text{Percent Error (PER)}=(\frac{(1+m')-{{2}^{m'}}}{{{2}^{m'}}})\times 100,\text{ 0}\le m'<\text{1}\)            (2)

Here, Percent Error (PER) is defined as the ratio of difference of percentage of approximated value and actual value and actual value. The approximation errors are obtained by Mitchell’s method for each sub-region [10]. The input format of ‘x’ for antilogarithmic conversion supposed to be x=0.m_-1 m₂ m_-3m_-4 up to x_-26. Here, we use only mantissa's four most significant bits (MSB) for adjustment of the concatenated result. Four bits of MSB can provide both accuracy and hardware complexity but three or five bits of MSB fail to provide an acceptable design trade-off. The mathematical formulation of proposed antilogarithmic conversion and error correction value is shown in Eqns. (3) and (4).

\(\begin{align}  & \text{Antilog(A)=}{{\text{2}}^{\text{A}}}\text{=}{{\text{2}}^{\text{p }\!\!'\!\!\text{ }}}\times {{2}^{x'}} \\ & ={{2}^{\text{p }\!\!'\!\!\text{ }}}(1+x'+\text{error correction value) } \\  & \text{Where 0}\le \text{x }\!\!'\!\!\text{ 1} \\\end{align}\)      (3)

\(\text{Error correction value = c = }\pm \sum\limits_{i}{{{2}^{-i}}}\)        (4)

where, ‘i’ is a positive integer value.

The proposed 11 or 17 regions have the proper selection of fractional region decides the error in that particular region. Here key factor is that deciding the fractional region in that way which generates an error which is multiple of power 2 or as near possible to that. Error decides the subtraction term. For hardware minimization, it gives an extra advantage to reported methods. We suggest best-optimized hardware as with less error. If we have selected other reasons then these may not be able to full-fill the design trade-off. For example, if N = 17, the ‘k’ can be partitioned into [0, 0.03), [0.03, 0.06), [0.06, 0.09), [0.09, 0.12), [0.12, 0.15), [0.15, 0.1875), [0.1875, 0.21875), [0.21875,0.25), [0.25, 0.3125), [0.3125, 0.375), [0.375,0.6875), [0.6875,0.75), [0.75,0.8125), [0.8125,0.860), [0.860,0.905), [0.905,0.955) and [0.955,1.00), respectively. Here, we partitioned 'k' in a manner that creates the minimum error. The fine-tuning process will be manually adjusted to get the minimum total percent errors after obtaining the optimal values of the error correction coefficient. We can also obtain antilogarithmic conversions for 11-region and 17-region. Antilogarithmic conversion is expressed in Eq. (5), with the compensating values by using some algorithm as given in Table 1 and Table 2.

\({{\text{A}}_{\text{proposed}}}\text{=}{{\text{2}}^{\text{p }\!\!'\!\!\text{ }}}\times {{2}^{x'}}\approx {{2}^{\text{p }\!\!'\!\!\text{ }}}(1+x'+\text{c), 0}\le \text{x }\!\!'\!\!<\text{ 1}\)       (5)

The values of ‘X’ are set to ‘0’ and the values of ‘c’ for each sub-region are given in Table 1 and Table 2.

Table 1. Parameters of the proposed converter using 11 region error correction schemes

According to Eq. (5), all the operations for compensation are based on additions or subtractions, achieving simple and feasible circuit implementations. It is noted in Eq. (3) that the term (1 + X’ + error correction value) multiplied by ‘2^p’’can be implemented with hard-wired connections of the corresponding bits of the values (1 + X’+ error correction value). Thus, multiplication and shift operations may be avoided. Since our algorithm produces the error correction values to consider lower percent errors.

Table 2. Parameters of the proposed converter using 17 region error correction schemes

Table 3. Conditions to add the 11-region corrected values

Table 4. Conditions to add the 17-region corrected values

Therefore, antilogarithmic converters can achieve high accuracy as compared to the reported methods [27, 31, 33]. The conditions are taken out as per the equation (5) to add the corrected values. These conditions are based on the values of ‘c’ for each sub-region is given in Table 1 and Table 2. With the help of Table 1 and Table 2, we draw the corrected values of 2^-4, 2^-5, 2^-6, and 2^-7 for 11-region and 17-region, which are shown in Table 3 and Table 4.

3.2 Hardware implementation

The proposed antilogarithm converter architectures for 11-region and 17-region with error correction schemes are shown in Figure 3(a), (b) and 4 (a) show the architecture of sub-component. Figure 3 (c) and 4 (b) show the main architecture of the 11-region and 17-region with an error correction scheme.

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(a)

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(b)

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(c)

Figure 3. (a), (b) are sub-components and (c) the proposed architecture of the 11-region error correction scheme

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(a)

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Figure 4. (a) sub-components and (b) the proposed architecture of the 17-region error correction scheme

The proposed antilogarithmic converter for 11-region and 17-region is found a significant gain in terms of accuracy and hardware. 11-region antilogarithmic converter gives a 7.36% less percentage error range in comparison of reported design given by Kuo et al. 17-region antilogarithmic converter provides 19.32% less percentage error range in comparison of the reported design is given by Kuo et al. for the 14- region constant compensation scheme. 11-region antilogarithmic converter gives 61% less ADP and 49.82% less energy in comparisons of reported 11-regions antilogarithmic converter. 17-region antilogarithmic converter gives 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed converter design is useful for real-time DSP and image applications.